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參數(shù)資料
| 型號： | HV7121B |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | CMOS IMAGE SENSOR With 8-bit ADC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 446K |
| 代理商： | HV7121B |
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HV7121B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 14 1999 Hyundai System IC
Division
n
Mode B
[1] :
shot
(shot mode) <
default value : 0b>
User can select continuous frame mode or snapshot mode according to application.
At the continuous frame mode, pixel data output is updated every VSYNC period. In order to set
snapshot mode, it this bit to ‘1’. In that case, just single frame of pixel data will be read out, then the
sensor stops operation. Snapshot mode can be used for the digital still camera applications.
n
Mode B[0] :
int_sel
(integration time unit select) <
default value : 0b>
This bit defines integration time unit i.e. line base or pixel clock base.
Default mode is line unit integration but at the bright condition or if you need precise exposure time
control, pixel mode is recommended. This bit related to integration time register 25h, 26h, and 27h.
Note : Actual integration time can be calculated using three integration time registers and pixel clock
period.
n pixel mode, integration time = (25h, 26h, 27h) * number of pixel period.
n line mode, integration time = (26h, 27h) * number of pixel per line * pixel period.
cf) number of pixel per line = 414 + HSYNC duration value
(3)
Mode C Register (Address 02h, default : 08h, R/W)
This register controls power down and color select.
n
Mode C[3] :
sw_enb
(software enable : active low)
(400*300 CMOS image sensor only) <
default value : 1b>
This bit is only exist in 400*300 CMOS image sensor chip to enable image sensor operation by
software. This bit has same function as ENB pin control.
t’s very useful for the applications that is needed want to reduce interface pin count to CMOS image
sensor. In that case, cannot ENB pin to VDD line and control the sensor using this bit.
n
Mode C[2] :
pwr_dn
(A/D converter power down) <
default value : 0b>
This bit controls power down of A/D converter when sleep mode(idle state) is set by ENB pin is low or
sw_enb
(Mode C[3]) is high. When set to high, A/D converter is turned on whenever ENB is low or
sw_enb
is high. When set to low, A/D converter is turned off always regardless ENB pin state or
sw_enb
state . But digital block goes to power down mode always when ENB is low regardless this bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HV7121B-COB | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:CMOS IMAGE SENSOR With 8-bit ADC |
| HV7121B-COF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:CMOS IMAGE SENSOR With 8-bit ADC |
| HV7121GP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sensor |
| HV712PG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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