
HV7121B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 21 1999 Hyundai System IC
Division
FRAME TIMING DIAGRAMS
There are two frame timing cases,
l
Integration Time < EffectiveWindowHeight * Scale
l
Integration Time > EffectiveWindowHeight * Scale
EffectiveWindowHeight is equal to the number of data lines generated in a frame and is defined to be selected by
if((RowStartAddress + WindowHeight + 1) <= (SensorArrayHeight)
EffectiveWindowHeight = WindowHeight;
else
EffectiveWidnowHeight = (SensorArrayHeight - RowStartAddress - 1);
For example, RowStartAddress = 200 and WindowHeight = 300, EffectiveWindowHeight is 113 and 113 data lines per
a frame are generated.
Note : The above selection logic is somewhat confusing in respect of general counting measure. It’s partly due to the
mixed use of indexing start points, i.e. ‘0’ and ‘1’ in the design. Therefore in order to avoid the confusion it is
desirable to just follows the equation when you estimate the frame rate.
Scale is selected according to Integration Time Mode by
If(PixelMode)
Scale = SensorArrayWidth; // For400*300 resolution chip, SensorArrayWidth is 414
else
Scale = 1;
When Integration Time > (EffectiveWindowHeight * Scale), next frame VSYNC does not follow immediately after
current frame’s last line has been produced. Instead, one of the following two idle time slots is inserted according to
Integration Time Mode before next frame VSYNC gets active.
SensorArrayHeight
[314]
SensorArrayWidth
[414]
RowStartAddress
[200]
WindowHeight
[300]
EffectiveWindowHeight
[113]
(0,0)