Pin No.
Pin Name
I/O
Description
58
BAL
I
Battery voltage detector input with pull-high resistor.
SRDY
I
SPI slave ready
with pull-high resistor. When the slave initiates the SPI transfer,
a high to low transition activates an interrupt. When the master
initiates the SPI transfer, a high to low transition trigger the
master to start the transfer.
This slave ready pin is a Schmitt trigger input
59
BAF
I
Battery fail indication input, active low.
60
DA_OUT
O
D/A converter output. This pin is an 8-bit D/A analog output
61
RSSI
I
RSSI output from IF circuit. This pin should be pulled high or low
externally when this pin is not used.
62
DI
I
POCSAG code input serial data. CMOS input with pull-high re-
sistor.
MISO
I
SPI master-in-slave-out
resistor for SPI communications.
this is the data input with pull-high
63
BS3
O
PLL power control enable, CMOS output
MOSI
O
SPI master-out-slave-in
nications.
this is the data output for SPI commu-
64
BS2
O
RF quick charge control enable, CMOS output
SCK
I/O
SPI serial clock
transfer. If HT9580 is in the master mode, the SCK is output
clock. Otherwise, SCK is input clock if HT9580 is in the slave
mode.
the SCK signal is used to synchronize the data
65
BS1
O
Pager receiver power control enable output, CMOS output
SS
O
SPI slave select
transfer.
this signal is used to enable the SPI slave for
66
TS
I
Decoder test mode input pin, active low with pull-high resistor.
72~67
PA0~PA5
I/O
General Input/Output Port A. These ports can be programmed to
have a wake-up capability for applications in keyboard operations
or as normal I/O. Also the input cell structures are all Schmitt
trigger types and can be selected between CMOS or CMOS with
pull-high resistors.
73
RESET
I
Schmitt trigger reset input, active low.
74
TSC
I
C test mode input pin, active low with internal pull-high resis-
tor. The test circuit will be activated when this pin pulls low.
75
TS1
I
Decoder test mode input pin, active low with pull-high resistor.
Theinternaltestmodewillbeactivatedwhenthispinpullslow.
77
76
OSC1
OSC2
I
O
OSC1 and OSC2 are connected to an RC network to form a main
clock oscillator
80
79
X1
X2
I
O
X1andX2areconnectedtoacrystaltoformaninternallowpower
clock oscillator (32.768kHz, 76.8kHz, or 153.6kHz)
HT9580
5
April 28, 2000
Preliminary