Configuration register
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0000H
Config.
HALT
CLK_SEL
OSC_MOD
LPM
RTC
BZ_CLK
MDUT
MGEN
0001 0000
HT9580
10
April 28, 2000
Preliminary
Oscillator configuration
There are two clock source input pins on the
chip, the main clock and the pager decoder in-
put clock. The main clock is generated by an RC
network. The system clock may be the OSC in-
put or the X1-clock depending on bit
CLK_SEL . The pager decoder input clock co-
mes from two external pins, X1 and X2. The fre-
quency of the sub-clock will be double that of
the X1, X2 input clock. The OSC1 main clock
will be generated from an RC network that
needs an external resistor (see Application Cir-
cuit). The system clock may be X1-clock, DF or
RC clock. If no higher frequency (RC) is needed,
the external resistor between OSC1 and OSC2
can be removed. The system clock can be
switched by bit CLK_SEL . If CLK_SEL =0
(POR State), the system clock will be X1-clock.
In other cases, with CLK_SEL =1, the OSC in-
put clock will be the system clock. The clock
switching function will assist software pro-
grammers to change the C system clock with-
in an adequate time if necessary. The
OSC_MOD bit selects the OSC input clock to
be either RC or DF. If OSC_MOD is set to
low thentheRCconfigurationisselected,oth-
erwise the DF application is selected. The pro-
grammer should note that the condition of
CLK_SEL , HALT and OSC_MOD assures
that the system clock is working properly. It is
recommended that the OSC clock source is ei-
ther DF or RC. If DF and RC are necessary, it is
required to switch the system clock to X1-clock
before switching between DF and RC. Then
switch the system clock back to the OSC input
by using bit CLK_SEL if the switching action of
DF and RC is complete. Before enter HALT
mode, the system clock must select X1-clock.
The HT9580 will generate two RTC frequen-
cies, 1Hz and 2Hz respectively, determined by
bit RTC. If the bit is logic low, the 1Hz RTC fre-
quency will be selected, otherwise the 2Hz RTC
frequency will be selected. The RTC counter is
enabled/disabled by bit RTCEN and can be
maskedornotmaskedasdeterminedbythe bit
RTCMSK of the interrupt control register
9
' B
9 = 9
9
C
C
-
A =
C B
C 4 3
D 3
3 #
B # $4 4
3
'
$
' B
9
4 3
3 # B
' B
3
- E F $ 9 3
) - E F $ 9 3
$ 3
RTC block diagram