Pin Description
Pin No.
Pin Name
I/O
Description
1, 25, 56
VDD
Positive power supply
2
LCD_CS1
O
LCD driver chip select control (for slave LCD driver)
3
LCD_CS0
O
LCD driver chip select control (for master LCD driver)
4
LCD_CL
O
LCD driver clock output
5
LCD_A0
O
LCD driver data/command select control
6
LCD_RW
O
LCD Driver Read/Write signal output
7
LCD_E
O
LCD driver enable clock control
15~8
D0~D7
I/O
8-bit, tristate, bidirectional I/O data bus.
16
R/W
O
Read/Write signal output
17
SRAM_CE
O
SRAM chip Enable. This signal is generated from the HT9580 to
provide read or write timing for external SRAM devices. (See Ap-
plication Circuit)
18
MASK_CE
O
Mask ROM Chip Enable. This signal is generated from the
HT9580 to provide read timing for external Mask ROM devices.
(See Application Circuit)
19
OE
O
Mask ROM or SRAM Output Enable. This signal is generated
from the HT9580 to provide read timing for external Mask ROM
and SRAM devices. (See Application Circuit)
20
PSEN
O
Program Store Enable. This pin is used to connect the OE and CE
pins of the external 44 Kbytes program ROM when the
MODE_P internal pad is connected to VSS. (See note)
21~24
RA17~RA14
O
Extended address bus pins
26
P_MODE
I
Internal or external program ROM selection without pull-high re-
sistor. If the pin connects to VDD, the internal program ROM will
be fetched (normal type), otherwise the external program ROM
will be fetched when the pin connects to VSS (Romless).
27, 57, 78 VSS
Negative power supply
43~28
A0~A15
O
Address bus pins. This is used for memory and I/O exchanges on
the data bus.
44
TMR1
I
Schmitt trigger input for timer1 counter with pull-high resisor.
45~52
PB0~PB7
I/O
General Input/Output Port B. The input cell structures can be se-
lected as CMOS or CMOS with pull-high resistors.
53~54
PC0~PC1
I/O
General Input/Output Port C. The input cell structures can be se-
lected as CMOS or CMOS with pull-high resistors.
55
BZ
O
Buzzer non-inverting BZ output
HT9580
4
April 28, 2000
Preliminary