參數(shù)資料
型號: HT9580
廠商: Holtek Semiconductor Inc.
英文描述: Character Pager Controller
中文描述: 字符傳呼機(jī)控制器
文件頁數(shù): 42/63頁
文件大?。?/td> 444K
代理商: HT9580
HT9580
42
April 28, 2000
Preliminary
CPU Core
The HT9580 is a high performance pager con-
troller specifically designed for use in new gen-
eration radio pagers. It is based on the M6502
core. The 6502 Microprocessor offers complete
hardware and software capability with existing
6500seriesofproductsaswellassignificanten-
hancements.
Instruction register and decoder
Instructions fetched from memory are gated
onto the internal bus. These instructions are
latched into the instruction register then de-
coded, along with timing and interrupt signals,
to generate control signals for the various regis-
ters.
Timing control unit
The timing control unit keeps track of the in-
struction cycle being monitored. The unit is set
to 0 each time an instruction fetch is executed
and is advanced at the beginning of each input
clock pulse for as many cycles as required to
complete the instruction. Each data transfer
between registers depends upon decoding the
contents of both the Instruction Register and
the Timing Control Unit. There are three major
clocks in the C as follows:
Phase 2 In (PHI2 (IN))
This signal is from the OSC1 input pin of
HT9580. The PHI1 (OUT) and PHI2 (OUT)
are derived from this signal.
Phase 2 Out (PHI2 (OUT))
This signal is generated from PHI2 (IN).
PHI2 (IN) provides the system timing. There
is a slight delay from PHI2 (IN).
Phase 1 Out (PHI1 (OUT))
Inverted PHI2 (OUT) signal. There is a slight
delay from PHIN2 (IN).
Read/write
This signal is normally in a high state indicat-
ing that the
C is reading data from the data
bus memory. In the low state the data bus has
valid data from the
C to be stored at the ad-
dressed memory location.
Parameter
Description
t
cyc
Clock cycle time (min)
t
ad
Address delay time
t
ah
Address hold time
t
dis
Read data in setup time
t
dih
Read data in hold time
t
dod
Write data out delay time
t
doh
Write data out hold time
t
denbd
DATAEN delay time
t
wed
WE_N delay time
t
syd
SYNC delay time
t
syh
SYNC hold time
t
vd
VPB delay time
t
vh
VPB hold time
t
sos
SOB_N setup time
t
soh
SOB_N hold time
t
rds
RDY setup time
t
rdh
RDY hold time
t
ress
RES_N setup time
t
resh
RES_N hold time
Timing parameter annotations
Arithmetic and logic unit
All arithmetic and logic operations take place
within the ALU including incrementing and
decrementing internal registers (except for the
program counter). The ALU has no internal
memory and is used only to perform logical and
transient numerical operations.
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