參數(shù)資料
型號(hào): HT9580
廠商: Holtek Semiconductor Inc.
英文描述: Character Pager Controller
中文描述: 字符傳呼機(jī)控制器
文件頁(yè)數(shù): 12/63頁(yè)
文件大小: 444K
代理商: HT9580
HT9580
12
April 28, 2000
Preliminary
The WDT 7-bit counter is programmed by bits
WS0~WS2. The division ratio for the counter is
listed in the table.
WS2
WS1
WS0
Division
Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
The other pair TMR0_PR0 and TMR0_PR1
are used to select the prescaler ratio for timer0.
The definition is shown in the table.
TMR0_PR1
TMR0_PR0
TMR0
Prescaler
Ratio
0
0
1/4
0
1
1/8
1
0
1/16
1
1
1/32
Buzzer generator registers
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0003H
BZ-L
BZL7
BZL6
BZL5
BZL4
BZL3
BZL2
BZL1
BZL0
0000 0000
0004H
BZ-H
BZH7
BZH6
BZH5
BZH4
BZH3
BZH2
BZH1
BZH0
0000 0000
The buzzer generator is composed of a 16-bit
PFDcounterandadutycyclecontrol.Thecoun-
ter value is set by two registers, namely BZ-H
and BZ-L. The source for this generator may be
the system clock or the X1-clock. The buzzer
generator is enabled/disabled by the register
bit
MGEN
in the configuration regis-
ter(0000H). When this bit is set high, the
buzzer generator is activated. There is another
bit in the configuration register(0000H) which
controls the buzzer output volume, bit
MDUT . If the bit is logic high, the output of
the BZ will be modulated by the X1-clock. The
clock source of the buzzer is selected by bit
BZ_CLK . When BZ_CLK=0, the clock source
is the system clock. On the other hand, when
BZ_CLK=1, the value of the selector will be the
X1-clock.
The truth table for enabling/disabling the
buzzer generator is shown in the table.
1
0
MGEN
Enable the
buzzer generator
Disable the
buzzer generator
' B
B # $
8 "
. B # $
"& '
:
)
: $ B 3
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