HT46R23/HT46C23
Rev. 1.60
21
May 3, 2004
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Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
trol register clears HAAS bit. If the address is not match,
this bit is reset to 0 . The HBB bit is set to respond the
I
2
C Bus is busy. It mean that a START signal is de-
tected. This bit is reset to 0 when the I
2
C Bus is not
busy. It means that a STOP signal is detected and the
I
2
C Bus is free. The SRW bit defines the read/write com-
mand bit, if the calling address is match. When HAAS is
set to
whether the device is working in transmit or receive
1 , the device check SRW bit to determine
mode.WhenSRWbitisset 1 ,itmeansthatthemaster
wants to read data from I
2
C Bus, the slave device must
write data to I
2
C Bus, so the slave device is working in
transmit mode. When SRW is reset to 0 , it means that
the master wants to write data to I
2
C Bus, the slave de-
vice must read data from the bus, so the slave device is
working in receive mode. The RXAK bit is reset 0 indi-
cates an acknowledges signal has been received. In the
transmit mode, the transmitter checks RXAK bit to know
the receiver which wants to receive the next data byte,
so the transmitter continue to write data to the I
2
C Bus
until the RXAK bit is set to 1 and the transmitter re-
leases the SDA line, so that the master can send the
STOP signal to release the bus.
The HADR bit7-bit1 define the device slave address. At
the beginning of transfer, the master must select a de-
vice by sending the address of the slave device. The bit
0 is unused and is not defined. If the I
2
C Bus receives a
start signal, all slave device notice the continuity of the
8-bit data. The front of 7 bits is slave address and the
first bit is MSB. If the address is match, the HAAS status
bit is set and generate an I
2
C Bus interrupt. In the ISR,
the slave device must check the HAAS bit to know the
I
2
C Bus interrupt comes from the slave address that has
match or completed one 8-bit data transfer. The last bit
ofthe8-bitdataisread/writecommandbit,itrespondsin
SRW bit. The slave will check the SRW bit to know if the
master wants to transmit or receive data. The device
check SRW bit to know it is as a transmitter or receiver.
Bit7~Bit1
Bit0
Slave Address
Note:
means undefined
HADR Register
The HDR register is the I
2
C Bus input/output data regis-
ter. Before transmitting data, the HDR must write the
data which we want to transmit. Before receiving data,
the device must dummy read data from HDR. Transmit
or Receive data from I
2
C Bus must be via the HDR reg-
ister. At the beginning of the transfer of the I
2
C Bus, the
devicemustinitialthebus,thefollowingarethenotesfor
initialing the I
2
C Bus.