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參數(shù)資料
| 型號： | HT46C23 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | A/D Type 8-Bit MCU |
| 中文描述： | 的A / D型8位微控制器 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 348K |
| 代理商： | HT46C23 |
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HT46R23/HT46C23
Rev. 1.60
11
May 3, 2004
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external sig-
nal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30k
to 750k . The system clock, divided
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating fre-
quency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDToscillator still works with a
period of approximately 65 s@5V. The WDT oscillator
can be disabled by options to conserve power.
Watchdog Timer
WDT
TheclocksourceoftheWDTisimplementedbyandedi-
cated RC oscillator (WDT oscillator) or instruction clock
(system clock divided by 4) decided by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The watchdog timer can be disabled by
an option. If the watchdog timer is disabled, all the exe-
cutions related to the WDT result in no operation.
Once an internal WDT oscillator (RC oscillator with pe-
riod 65 s/@5V normally) is selected, it is divided by
2
12
~2
15
(by options to get the WDT time-out period).
The minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with tem-
perature, VDD and process variations. By selection the
WDT options, longer time-out periods can be realized. If
theWDTtime-outisselected2
15
,themaximumtime-out
period is divided by 2
15
~2
16
about 2.1s~4.3s.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO. Whereas in the halt
mode, the overflow will initialize a warm reset only the
PCandSPareresettozero.ToclearthecontentsofWDT,
three methods are adopted; external reset (a low level to
RES), software instructions, or a HALT instruction. The
softwareinstructionsincludeCLRWDTandtheotherset
CLRWDT1andCLRWDT2.Ofthesetwotypesofinstruc-
tion, only one can be active depending on the options
CLR WDT times selection option . If the CLR WDT is
selected (i.e. CLRWDTtimes equal one), any execution of
the CLR WDTinstruction will clear the WDT. In case CLR
WDT1 and CLRWDT2 arechosen(i.e.CLRWDTtimes
equal two), these two instructions must be executed to
cleartheWDT;otherwise,theWDTmayresetthechipbe-
cause of time-out.
If the WDT time-out period is selected f
s
/2
12
(by options),
the WDT time-out period ranges from f
s
/2
12
~f
s
/2
13
, since
the CLR WDT or CLR WDT1 and CLR WDT2 in-
structions only clear the last two stages of the WDT.
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7
System Oscillator
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( =
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,
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0
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Watchdog Timer
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