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參數(shù)資料
| 型號： | HT46C23 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | A/D Type 8-Bit MCU |
| 中文描述： | 的A / D型8位微控制器 |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 348K |
| 代理商： | HT46C23 |
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HT46R23/HT46C23
Rev. 1.60
16
May 3, 2004
Each line of port A has the capability of waking-up the
device. The highest 3-bit of port C and 6-bit of port D are
not physically implemented; on reading them a 0 is re-
turned whereas writing then results in a no-operation.
See Application note.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by the timer/event
counter overflow signal. The input mode always remain-
ing its original functions. Once the PFD option is se-
lected, the PFD output signal is controlled by PA3 data
register only. Writing 1 to PA3 data register will enable
the PFD output function and writing 0 will force the
PA3 to remain at
shown below.
0 . The I/O functions of PA3 are
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
PA3
Logical
Input
Logical
Output
Logical
Input
PFD
(Timer on)
Note:
The PFD frequency is the timer/event counter
overflowfrequencydividedby2.
The PA4, PA5, PA6 and PA7 are pin-shared with TMR,
INT, SDA and SCL pins respectively.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1. If the PWM function is
enabled, the PWM0/PWM1 signal will appear on
PD0/PD1 (if PD0/PD1 is operating in output mode).
Writing 1 to PD0/PD1 data register will enable the
PWM0/PWM1 output function and writing 0 will force
the PD0/PD1 to remain at
PD0/PD1 are as shown.
0 . The I/O functions of
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
PD0
PD1
Logical
Input
Logical
Output
Logical
Input
PWM0
PWM1
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
PWM
The microcontroller provides 2 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1. The PWM channels have their data registers
denoted as PWM0 (1AH) and PWM1 (1BH). The fre-
quency source of the PWM counter comes from f
SYS
.
The PWM registers are two 8-bit registers. The wave-
forms of PWM outputs are as shown. Once the
PD0/PD1 are selected as the PWM outputs and the out-
put function of PD0/PD1 are enabled (PDC.0/PDC.1
= 0 ), writing 1 to PD0/PD1 data register will enable
the PWM output function and writing 0 will force the
PD0/PD1 to stay at 0 .
A(6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2.
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~3)
Duty Cycle
Modulation cycle i
(i=0~3)
i<AC
DC+1
64
i AC
DC
64
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle 0 ~ modulation cycle 1).
Eachmodulationcyclehas128PWMinputclockperiod.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
The group 2 is denoted by AC which is the value of
PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
Modulation cycle i
(i=0~1)
i<AC
DC+1
128
i AC
DC
128
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
f
SYS
/64 for (6+2) bits mode
f
SYS
/128 for (7+1) bits mode
f
SYS
/256
[PWM]/256
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相關代理商/技術參數(shù) |
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