參數(shù)資料
型號: HT46C23
廠商: Holtek Semiconductor Inc.
英文描述: A/D Type 8-Bit MCU
中文描述: 的A / D型8位微控制器
文件頁數(shù): 15/48頁
文件大?。?/td> 348K
代理商: HT46C23
HT46R23/HT46C23
Rev. 1.60
15
May 3, 2004
(Label
Function
PSC0~
PSC2
0~2
To define the prescaler stages, PSC2,
PSC1, PSC0=
000: f
INT
=f
SYS
001: f
INT
=f
SYS
/2
010: f
INT
=f
SYS
/4
011: f
INT
=f
SYS
/8
100: f
INT
=f
SYS
/16
101: f
INT
=f
SYS
/32
110: f
INT
=f
SYS
/64
111: f
INT
=f
SYS
/128
TE
3
To define the TMR active edge of timer/
event counter
(0=active on low to high;
1=active on high to low)
TON
4
To enable or disable timer counting
(0=disabled; 1=enabled)
5
Unused bits, read as 0
TM0
TM1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC Register
Input/Output Ports
There are 23 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction MOV
A,[m] (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under soft-
ware control. To function as an input, the corresponding
latch of the control register must write 1 . The input
source also depends on the control register. If the con-
trol register bit is 1 , the input will read the pad state. If
the control register bit is 0 , the contents of the latches
will move to the internal bus. The latter is possible in the
read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H or 18H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
1
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Input/Output Ports
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