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參數(shù)資料
| 型號： | HT46C23 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | A/D Type 8-Bit MCU |
| 中文描述： | 的A / D型8位微控制器 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 348K |
| 代理商： | HT46C23 |
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HT46R23/HT46C23
Rev. 1.60
10
May 3, 2004
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC0), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC0),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a sub-
routine call to location 0CH will occur. The related inter-
rupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
Register Bit No. Label
Function
INTC0
(0BH)
0
EMI
Controls the master (global)
interrupt
(1=enabled; 0=disabled)
1
EEI
Controlstheexternalinterrupt
(1=enabled; 0=disabled)
2
ETI
Controls the timer/event
counter interrupt
(1=enabled; 0=disabled)
3
EADI
Controls the A/D converter
interrupt
(1=enabled; 0=disabled)
4
EIF
Externalinterruptrequestflag
(1=active; 0=inactive)
5
TF
Internal timer/event counter
request flag
(1=active; 0=inactive)
6
ADF
A/D converter request flag
(1=active; 0=inactive)
7
Unused bit, read as 0
INTC0 Register
The I
2
C Bus interrupt is initialized by setting the I
2
C Bus
interrupt request flag (HIF; bit 4 of INTC1), caused by a
slaveaddressmatch(HAAS= 1 ) or one byte of data trans-
fer is completed. When the interrupt is enabled, the stack
is not full and the HIF bit is set, a subroutine call to location
10H will occur. The related interrupt request flag (HIF) will
be reset and the EMI bit cleared to disable further inter-
rupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
RETI may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter Overflow
2
08H
A/D Converter Interrupt
3
0CH
Serial bus interrupt
4
10H
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), A/D converter request
flag (ADF), the I
2
C Bus interrupt request flag (HIF), en-
able timer/event counter bit (ETI), enable external inter-
rupt bit (EEI), enable A/D converter interrupt bit (EADI),
enable I
2
C Bus interrupt bit (EHI) and enable master in-
terrupt bit (EMI) constitute an interrupt control register 0
(INTC0) and an interrupt control register 1 (INTC1)
which are located at 0BH and 1EH in the data memory.
EMI, EEI, ETI, EADI, EHI are used to control the en-
abling/disabling of interrupts. These bits prevent the re-
quested interrupt from being serviced. Once the
interrupt request flags (TF, EIF, ADF, HIF) are set, they
will remain in the INTC0 and INTC1 register until the in-
terrupts are serviced or cleared by a software instruc-
tion.
Register Bit No. Label
Function
INTC1
(1EH)
0
EHI
ControlstheI
2
CBusinterrupt
(1= enabled; 0= disabled)
1~3
Unused bit, read as 0
4
HIF
I
2
CBusinterruptrequestflag
(1= active; 0= inactive)
5~7
Unused bit, read as 0
INTC1 Register
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
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PDF描述 |
|---|---|
| HT46C24 | A/D Type 8-Bit MCU |
| HT46R24 | A/D Type 8-Bit MCU |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT46C232 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:A/D Type 8-Bit MCU |
| HT46C24 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:A/D Type 8-Bit MCU |
| HT46C46 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective A/D Type 8-Bit MCU |
| HT46C46E | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective A/D Type 8-Bit MCU |
| HT46C47 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective A/D Type 8-Bit MCU |
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