參數(shù)資料
型號(hào)： HSP50415VI
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CABLE ASSEMBLY; 75 OHM TNC MALE TO 75 OHM TNC MALE; 75 OHM, RG6A/U COAX
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, PLASTIC, MQFP-100
文件頁數(shù)： 4/29頁
文件大?。?/td> 229K
代理商： HSP50415VI
4-4
Pin Descriptions
NAME
TYPE
DESCRIPTION
VDD
-
Digital power.
GND
-
Digital ground.
DVDD
-
DAC digital power.
DGND
-
DAC digital ground.
AVDD
-
DAC analog power.
AGND
-
DAC analog ground.
PVDD
-
PLL analog power.
PGND
-
PLL analog ground.
PLLRC
I
PLL loop filter provides for the addition of less expensive RC components in place of a crystal oscillator. The
recommended values for this pin are detailed in the ‘System CLK Generation’ section.
CLK
I
System and DAC clock input when APLL not in use, otherwise it is the reference to the APLL.
SYSCLK/2
O
Sample Clock Divided by Two. All digital output data and status pins are output from this clock. The polarity of
SYSCLK/2 may be programmed via Register 2 bit-3.
2XSYMCLK
O
Tristatable Symbol NCO Clock Output Multiplied by Two. The polarity of 2XSYMCLK may be programmed via
register 2 bit-15.
REFCLK
I
External digital PLL reference clock input.
DIN<15:0>
I
Data Bus. The DIN<15:0> bus loads the input data.
DATACLK
I
Asynchronous data clock for DIN<15:0>.
TXEN
I
DIN<15:0> may be optionally gated with the TXEN pin (burst mode) or input free-running as defined by register 2
bits 18-17. The polarity of TXEN may be programmed via register 2 bit-5.
ISTRB
I
Data samples are input as I then Q serially with the ISTRB pin active with the I sample. The polarity of ISTRB may
be programmed via Register 2 bit-4.
CDATA<7:0>
I/O
μ
P Bidirectional Data Bus. The CDATA<7:0> data bus is used for loading the configuration data and sample vectors
for modulation. CDATA7 is the MSB.
RD
I
μ
P Read control input.
WR
I
μ
P Write strobe input.
CE
I
Chip enable input.
ADDR<2:0>
I
μ
P Address Bus. The ADDR<2:0> bus is used for addressing the proper registers for loading the configuration data
and sample vectors for modulation. ADDR2 is the MSB.
INTREQ
O
Tristatable Active High Interrupt Request Output. The INTREQ output is enabled via register 2 bit-8. Register 9 bits
6-0 enable individual events for INTREQ.
RESET
While the RESET input is asserted (driven low), all processing halts and the WPM is reset. A software reset is also
available via register 10
H
.
IOUT<13:0>
O
Tristatable In-Phase Output Samples. IOUT<13:0> outputs are enabled via register 2 bit-7.
QOUT<13:0>
O
Tristatable Quadrature Output Samples. QOUT<13:0> outputs are enabled via register 2 bit-6. The QOUT<13:0>
outputs are not available on the MQFP package.
FEMPT,
FOVRFL,
FFULL
O
Tristatable Status Flags for FIFO Level Monitoring. These outputs are enabled via register 2 bits 13-11. FIFO status
thresholds and control are configured via register 2 bits 23-16.
LOCKDET
O
Tristatable Status Flag of the Digital PLL. This may be used to generate an interrupt request via INTREQ.
The LOCKDET output is enabled via register 2 bit-10.
IOUTA,
QOUTA
O
Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1.
IOUTB,
QOUTB
O
Complementary Current Outputs of the Device. Full scale output current is achieved on the complementary outputs
when all input bits are set to binary 0.
HSP50415
相關(guān)PDF資料
PDF描述
HSP50415EVAL1 HSP50415EVAL1 Evaluation Kit
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HSP9520CS Multilevel Pipeline Registers
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參數(shù)描述
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