參數(shù)資料
型號： HSP50415VI
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CABLE ASSEMBLY; 75 OHM TNC MALE TO 75 OHM TNC MALE; 75 OHM, RG6A/U COAX
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, PLASTIC, MQFP-100
文件頁數(shù)： 27/29頁
文件大?。?/td> 229K
代理商： HSP50415VI
4-27
DATACLK Low, T
DCL
5
-
-
ns
Setup Time, T
DS
DIN<15:0>, TXEN, ISTRB to DATACLK,
(Note 1)
8
-
-
ns
Hold Time, T
DH
DIN<15:0>, TXEN, ISTRB from DATACLK,
(Note 1)
0
-
-
ns
AC CHARACTERISTICS: DIGITAL STATUS / DATA
REFCLK Frequency, F
RCK
-
-
CLK / 4
MHz
REFCLK High, T
RCH
5
-
-
ns
REFCLK Low, T
RCL
5
-
-
ns
Digital Status & Output Data Delay, T
DO
From SYSCLK/2
Includes IOUT<13:0>, FIFO status pins,
LOCKDET and INTREQ., (Note 1)
-
-
5
ns
ANALOG OUTPUT PERFORMANCE:
Resolution
12
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 4)
-
±
1
-
LSB
Differential Linearity Error, DNL
(Note 4)
-
±
0.5
-
LSB
Offset Error, I
OS
(Note 4)
-0.025
+0.025
% FSR
Offset Drift Coefficient
(Note 4)
-
0.1
-
ppm
FSR/
o
C
Full Scale Gain Error, FSE
With External Reference (Notes 3, 4)
-10
±
2
+10
% FSR
With Internal Reference (Notes 3, 4)
-10
±
1
+10
% FSR
Full Scale Gain Drift
With External Reference (Note 4)
-
±
50
-
ppm
FSR/
o
C
With Internal Reference (Note 4)
-
±
100
-
ppm
FSR/
o
C
Full Scale Output Current, I
FS
2
-
20
mA
Output Capacitance
(Note 1)
-
30
-
pF
Output Voltage Compliance Range
(Note 1, 4)
-1.0
-
1.25
V
Gain Matching Between Channels
-8
-
+8
% FSR
Offset Matching Between Channels
-
±
0.05
-
% FSR
Phase Matching Between Channels
(Note 1)
-
±0.
5
-
Degrees
VOLTAGE REFERENCE:
Internal Reference Voltage, V
REF
-
1.23
-
V
Internal Reference Voltage Drift
(Note 1)
-
±
40
-
ppm
/
o
C
Internal Reference Output Current Sink/Source
Capability
(Note 1)
-
±
0.1
-
μ
A
Reference Input Impedance
(Note 1)
-
1
-
M
Reference Input Multiplying Bandwidth
(Notes 1, 4)
-
1.4
-
MHz
NOTES:
1. Parameter guaranteed by design or characterization and not production tested.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
3. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 625
μ
A). Ideally the
ratio should be 32.
4. See ‘Definition of DAC Specifications’ section.
Electrical Specifications
VDD = +3.3V
±
5%, T
A
= -40
o
C to 85
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
HSP50415
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