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參數(shù)資料
| 型號： | HSP50110JI-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital Quadrature Tuner |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 199K |
| 代理商： | HSP50110JI-52 |
3-232
Functional Description
The Digital Quadrature Tuner (DQT) provides many of the
functions needed for digital demodulation including: carrier
LO generation, mixing, low-pass filtering, baseband
sampling, baseband AGC, and IF AGC error detection. A
block diagram of the DQT is provided in Figure 1. The DQT
processes a real or complex input at rates up to 52 MSPS.
The digitized IF is input to the Synthesizer/Mixer where it is
multiplied by a quadrature LO of user programmable
frequency. This operation tunes the channel of interest to DC
where it is extracted by the Low Pass FIR Filtering section.
The filter bandwidth is set through a user programmable
decimation factor. The decimation factor is set by the Re-
Sampler which controls the baseband sampling rate. The
baseband sample rate can be adjusted by an external
symbol tracking loop via a serial interface. Similarly, a serial
interface is provided which allows the frequency of the
Synthesizer/Mixer’s NCO to be controlled by an external
carrier tracking loop. The serial interfaces were designed to
mate with the output of loop filters on the HSP50210 Digital
Costas Loop.
The DQT provides an input level detector and an internal
AGC to help maintain the input and output signal
magnitudes at user specified levels. The input level detector
compares the input signal magnitude to a programmable
level and generates an error signal. The error signal can be
externally averaged to set the gain of an amplifier in front of
the A/D which closes the AGC loop. The output signal level
is maintained by an internal AGC loop closed around the
Low Pass Filtering. The AGC loop gain and gain limits are
programmable.
Input Controller
The input controller sets the input sample rate of the
processing elements. The controller has two operational
modes which include a Gated Input Mode for processing
sample rates slower than CLK, and an Interpolated Input
Mode for increasing the effective time resolution of the
samples. The mode is selected by setting bit 1 of the I/O
Formatting Control Register in Table 10.
In Gated Input Mode, the Input Enable (ENI) controls the
data flow into the input pipeline and the processing of the
internal elements. When this input is sampled “l(fā)ow” by CLK,
the data on IIN0-9 and QIN0-9 is clocked into the processing
pipeline; when ENI is sampled “high”, the data inputs are
disabled. The Input Enable is pipelined to the internal
COMPLEX
MULTIPLIER
LEVEL
DETECT
F
O
R
M
A
T
LEVEL
DETECT
LOOP
FILTER
RE-SAMPLER
NCO
SYNTHESIZER
NCO
SHIFT REG
MICROPROCESSOR INTERFACE
COS
SIN
IIN0-9
QIN0-9
HI/LO
PH0-1
CFLD
COF
SOF
COFSYNC
SOFSYNC
WR
RD
C0-7
10
10
CENTER
FREQUENCY
PHASE
OFFSET
32
8
SAMPLER CENTER
FREQUENCY
32
AGC THRESHOLD
THRESHOLD FOR
EXTERNAL AGC
LOWER LIMIT
UPPER LIMIT
LOOP GAIN
10
10
12
12
11
11
10
10
IOUT0-9
QOUT0-9
DECIMATING
FILTER
COMPENSATION
FILTER
Indicates data downloaded via microprocessor interface
SSTRB
SPH0-4
5
I
C
ENI
INPUT MODE
SYNTHESIZER/MIXER
SHIFT REG
RE-SAMPLER
DIVIDER
LOW PASS FILTERING
AGC
OEI
DATARDY
OEQ
CLK
CLK
A0-2
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF HSP50110
LOTP
HI/LO OUTPUT SENSE
INPUT FORMAT
COF EN
WORD WIDTH
SOF EN
WORD WIDTH
HSP50110
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| HSP50214VC | Programmable Downconverter |
| HSP50214VI | Programmable Downconverter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
| HSP50210JC-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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