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參數(shù)資料
| 型號： | HSP50110JI-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital Quadrature Tuner |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 199K |
| 代理商： | HSP50110JI-52 |
3-245
For added flexibility, the CFLD input provides an alternative
mechanism for transferring data from the Microprocessor
Interfaces’s Holding Registers to the Center Frequency
Register. When CFLD is sampled “high” by the rising edge
of clock, the contents of the Holding Registers are
transferred to the Center Frequency Register as shown in
Figure 23. Using this loading mechanism, an update of the
Center Frequency Register can be synchronized with an
external event. Caution should be taken when using the
CFLD since the Holding Register contents will be
transferred to the Center Frequency Register whenever
CFLD is asserted.
NOTE: CFLD should not be asserted
any sooner than 2 CLK’s following the last Holding
Register load.
As Shown in Figure 24, the next
Configuration Register can be loaded one CLK after CFLD
has been loaded on the rising edge of CLK.
The Microprocessor Interface can be used to read the upper
8 bits of the AGC Loop Filter Accumulator. The procedure for
reading the Loop Accumulator consists of first sampling the
loop accumulator by writing 9 to the Destination Address
Register and then reading the loop accumulator value on
C0-7 by asserting RD. The sampled value is enabled for
output on C0-7 by forcing RD “l(fā)ow” no sooner than 6 CLK’s
after the writing the Destination Register as shown in
Figure 25. The 8-bit output corresponds to the 3 exponent
bits and 5 fractional bits to the right of the binary point (see
Figure 3). The 3 exponent bits map to C7-5 with C7 being
the most significant. The fractional bits map to C4-0 in
decreasing significance from C4 to C0.
NOTE:
croprocessor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. While the microprocessor
waveforms are not required to be synchronous to CLK, they are shown as synchronous waveforms for clarity in the illustration.
These processor signals are representative. The actual shape of the waveforms will be set by the microprocessor used. Verify that the mi-
FIGURE 23. CONTROL REGISTER LOADING SEQUENCE
LOAD
CONFIGURATION
DATA
LOAD ADDRESS OF
TARGET CONTROL
REGISTER AND
WAIT 4 CLKs
LOAD NEXT
CONFIGURATION
REGISTER
WR
CLK
A0-2
C0-7
1
EARLIEST TIME
ANOTHER LOAD
CAN BEGIN
2
3
4
4
3
2
1
0
0
1
DON’T CARE
RD
P
S
NOTE:
The actual shape of the waveforms will be set by the microprocessor
used. Verify that the processor waveforms meet the parameters in
the Waveforms Section of this data sheet to ensure proper operation.
The Processor waveforms are not required to be synchronous to
CLK. They are shown that way to clarify the illustration.
These processor signals are meant to be representative.
FIGURE 24. CENTER FREQUENCY CONTROL REGISTER
LOADING SEQUENCE USING CF LOAD
WR
0
1
2
3
LOAD
CONFIGURATION
DATA
1
CLK
A0-2
C0-7
LOAD NEXT
CONFIGURATION
REGISTER
0
1
2
2
3
NEXT CLK
FOLLOWING
CFLD
CFLD
WR
4
LOAD ADDRESS
OF TARGET
CONTROL REGISTER
AND WAIT 6 CLK’S
CLK
A0-2
C0-7
ASSERT RD
TO ENABLE DATA
OUTPUT ON C0-7
1
2
3
4
5
6
9
THREE-STATE
INPUT BUS
NOTE:
The actual shape of the waveforms will be set by the microprocessor
used. Verify that the processor waveforms meet the parameters in
the Waveforms Section of this data sheet to ensure proper operation.
The Processor waveforms are not required to be synchronous to
CLK. They are shown that way to clarify the illustration.
These processor signals are meant to be representative.
FIGURE 25. AGC READ SEQUENCE
RD
DON’T CARE
HSP50110
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| HSP50214VC | Programmable Downconverter |
| HSP50214VI | Programmable Downconverter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
| HSP50210JC-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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