參數(shù)資料
型號: HSP50110JI-52
廠商: HARRIS SEMICONDUCTOR
元件分類: 通信及網(wǎng)絡
英文描述: Digital Quadrature Tuner
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁數(shù): 18/24頁
文件大?。?/td> 199K
代理商: HSP50110JI-52
3-246
l
TABLE 6. CENTER FREQUENCY REGISTER
DESTINATION ADDRESS = 0
BIT
POSITIONS
FUNCTION
DESCRIPTION
31-0
Center Frequency
This register controls the center frequency of the Synthesizer/Mixer NCO. This 32-bit two’s complement
value sets the center frequency as described in the Synthesizer/Mixer Section. Center
F
C
F
S
H
Format: [XXXXXXXX]H
Range: (0000000 - FFFFFFF)H.
TABLE 7. SAMPLER CENTER FREQUENCY REGISTER
DESTINATION ADDRESS = 1
BIT
POSITION
FUNCTION
DESCRIPTION
31-0
Sampler Center
Frequency
This register controls the center frequency of the Re-Sampler NCO. This 32-bit value together with the
setting of a programmable divider set the decimation factor of the CIC Filter (see Re-Sampler and Low
Pass Filter Sections).
F
S
Format: [XXXXXXXX]H
Range: (0000000 - FFFFFFF)H.
TABLE 8. INPUT THRESHOLD REGISTER
DESTINATION ADDRESS = 2
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
Input Level Detector
Threshold
This register sets the magnitude threshold for the Input Level Detector (see Input Level Detector Section).
This 8-bit value is a fractional unsigned number whose format is given by:
2
0
. 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.
The possible threshold values range from 0 to 1.9961 (00 - FF)
H
. The magnitude range for complex inputs
is 0.0 - 1.4142 while that for real inputs is 0.0 - 1.0. Threshold values of greater than 1.4142 will never be
exceeded.
31-8
Reserved.
TABLE 9. AGC CONTROL REGISTER
DESTINATION ADDRESS = 3
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
AGC Level Detector
Threshold
Magnitude threshold for the AGC Level Detector (see AGC Section). The magnitude threshold is repre-
sented as an 8-bit fractional unsigned value with the following format:
2
0
. 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.
The possible threshold values range from 0 to 1.9961. However, the usable range of threshold values
span from 0 to 1.4142, since full scale outputs on both I and Q correspond to a magnitude of
. Thresholdvaluesofgreaterthan1.4142willforcetheAGCgaintotheupperlimit.
15-8
Loop Filter Upper Limit
(Maximum Gain)
Upper limit for Loop Filter’s accumulator (see AGC Section). The three most significant bits are the expo-
nent and the five least significant bits represent the mantissa (see Figure 3). The three exponent bits map
to bit positions 15-13 (15 is the MSB) and the five mantissa bits map to bit positions 12-8 (12 is the MSB).
(EEE.MMMMM)
2.
Lower limit for Loop Filter’s accumulator (see AGC Section). The format is the same as that for the upper
limit described above. The 3 exponent bits map to bit positions 23-21 (23 is the MSB) and the mantissa
bits map to bit positions 20-16 (20 is the MSB). (EEE.MMMMM)
2.
Programmable part of Loop Gain word (see AGC Section). The Loop Gain value increments or decre-
ments the Loop Filter’s Accumulator at bit positions 2
-6
through 2
-13
as shown in Figure 3. The 8-bit loop
gain is loaded into bit positions 31-24 (31 is the MSB and maps to the 2
-6
position in the Accumulator).
(GGGGGGGG)
2.
23-16
Loop Filter Lower Limit
(Minimum Gain)
31-24
Programmable Loop
Gain
Center Frequency
CF
H
-------
2
32
COF
H
=
=
SamplerCenter Frequency
SCF
H
---------------
2
32
H
SCOF
H.
=
=
I
2
Q
2
+
2
1.4142
=
=
HSP50110
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