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參數(shù)資料
| 型號： | HSP50110JI-52 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital Quadrature Tuner |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 199K |
| 代理商： | HSP50110JI-52 |
3-241
or 0.77 depending on whether the bypass, x/sin(x) or
(x/sin(x))
3
configuration is chosen. The Compensation Filter
output is then rounded and limited to a 10-bit output range
corresponding to bit positions 2
0
to 2
-9
.
Setting DQT Gains
The AGC and CIC Shifter gains are programmed to maintain
the output signal at a desired level. The gain range required
depends on the signal levels expected at the input and the A/D
backoff required to prevent signal + noise from saturating the
A/D. The signal level at the input is based on the input SNR
which itself is derived from the either output SNR or output
E
S
/N
0
. Below are two examples which describe setting the
gains using either an output SNR or E
S
/N
0
specification.
In applications based on the transmission of digital data, it is
useful to specify the DQT’s output in terms of E
S
/N
0
. The
following example uses this parameter and the others given in
Table 4 to show how the DQT’s gain settings can be derived.
First, the maximum and minimum input signal levels must be
determined. The maximum input signal level is achieved in a
noise free environment where the input signal is attenuated by
12dB as a result of the A/D backoff. The minimum input signal
is determined by converting the minimum output E
S
/N
0
specification into an Input SNR. Using the example parameters
in Table 4 the minimum input SNR is given by:
SNR
IN
= 10log
10
(E
S
/N
0
) + 10log
10
(Symbol Rate)
-10log
10
(NBW)
= -3dB + 10log
10
(0.5x32 x 10
3
) - 10log
10
(10 x 10
6
)
= -30.96dB
(EQ. 12)
NOTE: 10log
10
(x) is used because these items are power
related.
Thus, the minimum input signal will then be -42.96dB below
full scale (-30.96dB -12dB for A/D backoff). Note: in this
example the symbol rate is assumed to be one half of the
output sample rate (i.e., there are 2 samples per symbol).
The output signal is related to the input signal by:
S
OUT
= S
IN
x G
MIXER
x G
SCALER
x G
AGC
x
G
SHIFTER
x G
CIC
x G
COMP
Using this equation, limits for G
AGC
and G
SHIFTER
can be
determined from the minimum and maximum input signal
conditions as given below (all gains specified in dB):
(EQ.13)
(EQ. 14)
Min Input Level (Maximum Gain Required):
-6.02dB
≥
-42.96 - 6.02 - 216.74 + G
AGC
+ G
SHIFTER
+
20 x log((40 x 10
6
/32 x 10
3
)
3
) - 2.27
(EQ. 15)
Max Input Level (Minimum Input Gain Required)
-6.02dB
≤
-12 - 6.02 - 216.74 + G
AGC
+ G
SHIFTER
+
20 x log((40 x 10
6
/32 x 10
3
)
3
) - 2.27
(EQ. 16)
NOTE: 20log
10
(x) is used because these items are
amplitude related.
Solving the above inequalities for G
AGC
and G
SHIFTER
, the
gain range can be expressed as,
45.20dB < (G
AGC
+ G
SHIFTER
) < 76.16dB.
The shifter gain provides a programmable gain which is a
factor of 2. Since G
AGC
≥
1.0, G
SHIFTER
is set as close to
the minimum gain requirement as possible:
(EQ. 17)
G
SHIFTER
= 2
N
,
where
(EQ. 18)
N = floor(log
2
(10
(G
MIN
/20)
))
= floor(log
2
(10
(45.20/20)
)) = 7
The limits on the AGC gain can then be determined by
substituting the shifter gain into Equation 18 above. The
resulting limits are given by:
3.05dB < G
AGC
<34.02dB.
In some applications it is more desirable to specify the DQT
output in terms of SNR. This example, covers derivation of
the gain settings based on an output SNR of 15dB. The
other system parameters are given in Table 4.
(EQ. 19)
As in the previous examples the minimum and maximum
input signal levels must be determined. The minimum input
signal strength is determined by from the minimum output
SNR as given by:
SNR
IN
= SNR
OUT
- 10log(NBW) + 10log(B
N
x F
SOUT
)
= 15 - 10log(10 x 10
6
) + 10log(34.18 x 10
3
)
= -9.66dB
(EQ. 20)
TABLE 4. EXAMPLE SYSTEM PARAMETERS
PARAMETER
MAIN MENU
ITEM
SETTING
Input Sample Rate
(2)
40 MSPS
OutputSampleRate(F
SOUT
)(Notes1,2)
(8), (9)
32 KSPS
Input Filter Noise Bandwidth (NBW)
(10)
10MHz
Minimum Output E
S
/N
0
(15)
-3dB
Signal + Noise Backoff at A/D Input
(18), (19)
12dB
Output Signal Magnitude (0 to 1)
(21)
0.5
Number of CIC stages
(11)
3
Compensation Filter
(11)
(x/sin(x))
3
Noise Eq. Bandwidth of Comp. Filter
(B
N
*F
SOUT
)
N/A
34.18kHz
Input Type (Real/Complex)
(4)
Real
NOTES:
1. Two samples per symbol assumed.
2. Decimation = 40 MSPS/32 KSPS = 1250.
HSP50110
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50110JI-52Z | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDU - Rail/Tube |
| HSP50210 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Costas Loop |
| HSP50210JC-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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