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參數(shù)資料
| 型號： | HS-6664RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened 8K x 8 CMOS PROM |
| 中文描述： | 輻射加固8K的× 8的CMOS胎膜早破 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 222K |
| 代理商： | HS-6664RH |
DESIGN INFORMATION
(Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
851
HS-6664RH
Background Information Programming
The HS-6664 CMOS PROM is manufactured with all bits
containing a logical zero (output low). Any bit can be
programmed selectively to a logical one (output high) state
by following the procedure shown below. To accomplish this,
a programmer can be built that meets the specifications
shown, or use of an approved commercial programmer is
recommended.
Programming Sequence of Events
1. Apply a voltage of VDD1 to VDD of the PROM.
2. Read all fuse locations to verify that the PROM is blank
(output low).
3. Place the PROM in the initial state for programming:
E = VIH, P = VIH, G = VIL.
4. Apply the correct binary address for the word to be pro-
grammed. No inputs should be left open circuit.
5. After a delay of td, apply voltage of VIL to E (pin 20) to ac-
cess the addressed word.
6. The address may be held through the cycle, but must be
held valid at least for a time equal to td after the falling
edge of E. None of the inputs should be allowed to float
to an invalid logic level.
7. After a delay of td, disable the outputs by applying a volt-
age of VIH to G (pin 22).
8. After a delay of td, apply voltage of VIL to P (pin 27).
9. After delay of td, raise VDD (pin 28) to VDDPROG with a
rise time of tr. All outputs at VIH should track VDD within
VDD-2.0V to VDD+0.3V. This could be accomplished by
pulling outputs at VIH to VDD through pull-up resistors of
value Rn.
10. After a delay of td, pull the output which corresponds to
the bit to be programmed to VIL. Only one bit should be
programmed at a time.
11. After a delay of tpw, allow the output to be pulled to VIH
through pull-up resistor Rn.
12. After a delay of td, reduce VDD (pin 28) to VDD1 with a
fall time of tf. All outputs at VIH should track VDD with
VDD-2.0V to VDD+0.3V. This could be accomplished by
pulling outputs at VIH to VDD through pull-up resistors of
value Rn.
13. Apply a voltage of VIH to P (pin 27).
14. After a delay of td, apply a voltage of VIL to G (pin 22).
15. After a delay of td, examine the outputs for correct data.
If any location verifies incorrectly, it should be considered
a programming reject.
16. Repeat steps 3 through 15 for all other bits to be pro-
grammed in the PROM.
Post-Programming Verification
17. Place the PROM in the post-programming verification
mode:
E = VIH, G = VIL, P = VIH, VDD (pin 28) = VDD1.
18. Apply the correct binary address of the word to be veri-
fied to the PROM.
19. After a delay of td, apply a voltage of VIL to E (pin 20).
20. After a delay of td, examine the outputs for correct data.
If any location fails to verify correctly, the PROM should
be considered a programming reject.
21. Repeat steps 17 through 20 for all possible programming
locations.
Post-Programming Read
22. Apply a voltage of VDD2 = 4.0V to VDD (pin 28).
23. After a delay of td, apply a voltage of VIH to E (pin 20).
24. Apply the correct binary address of the word to be read.
25. After a delay of TAVEL, apply a voltage of VIL to E (pin
20).
26. After a delay of TELQV, examine the outputs for correct
data. If any location fails to verify correctly, the PROM
should be considered a programming reject.
27. Repeat steps 23 through 26 for all address locations.
28. Apply a voltage of VDD2 = 6.0V to VDD (pin 28).
29. Repeat steps 23 through 26 for all address locations.
Spec Number
518741
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相關代理商/技術參數(shù) |
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| HS-6664RH_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 8K x 8 CMOS PROM |
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