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參數(shù)資料
| 型號： | HI7188IN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV A/D 16BIT 8:1 MUX 44-MQFP |
| 標準包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 240 |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個差分，單極；8 個差分，雙極 |
14
A one channel example:
1. Channel 1 is sampled four times as labeled S1, S2, S3,
and S4 in Figure 12. One sample for each 90 degrees
quadrant of line cycle (quarter main cycle).
2. Each sample is equally spaced (From zero, S1 = 5 degrees,
S2 = 95 degrees, S3 = 185 degrees and S4 = 275 degrees).
3. Each sample is of the same duration of time.
4. Samples S1 and S3 (180 degrees later) will have the
equal magnitudes of line noise but have opposite signs.
5. Samples S2 and S4 (180 degrees later) will have the
equal magnitudes but opposite signs.
6. The HI7188 sums the samples S1, S3, S2 and S4 which
results in averaging the line noise signal to zero.
7. These four samples are placed, real time, in the 4x8 array
of registers used for LNR. The next quadrant sampled (S5)
replaces S1 in the running average. The new sample
replaced S1 at the same point on the line cycle, 5 degrees
but 360 degrees later. The line noise summation is still
zero. Now for every quarter main cycle thereafter, the LNR
will be updated and line noise free output will be available.
Calibration
Calibration is the process of adjusting the conversion data
based on known system offset and gain errors. For a
complete system calibration to occur, the on-chip
microcontroller must perform a three point calibration which
involves recording conversion results for three different input
conditions - “zero-scale,” “positive full-scale,” and “negative
full-scale”. With these readings, the HI7188 can null any
system offset errors and calculate the positive and negative
gain slope factors for the transfer function of the system. It is
CONVERSION CONTROL
SERIAL
INTERFACE
CLOCK
GENERATOR
OSC1 OSC2
CA
EOS
MODE
CS
RST
RSTIO
SDIO
SDO
SCLK
CONTROL
REGISTER
24
CALIBRATION
REGISTERS
AND CONTROL
16
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
24
INTEGRATING
FILTER
23
FROM
ANALOG
SECTION
1
LOGICAL
SEQ
UENCER
CCR REGISTERS
LOGICAL
CHANNEL
ADDRESS
FIGURE 11. DIGITAL BLOCK DIAGRAM
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
RAM0
RAM1
LOGICAL
CHANNELS
BYPASS
LNR
LINE NOISE FILTER
TIME
4
5
6 7
8
2 3
4
5
6
7
8
1
2
3
4
5
6 7 8
2 3
4
5
6
7
8
1
LINE NOISE
S1
S2
S3
S4
FIGURE 12. LINE NOISE CYCLE INCLUDING PATENTED TIME
SPACED INPUT SAMPLING
S5
HI7188
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