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參數(shù)資料
| 型號： | HI7188IN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV A/D 16BIT 8:1 MUX 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 240 |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)差分，單極；8 個(gè)差分，雙極 |
11
The conguration can be saved by writing the contents of the
CR, CCR and calibration RAMs to microprocessor system
memory (see Serial Interface section). After this has
occurred, the conguration can easily be restored back to
the HI7188 in the event of power failure or reset.
Analog Section Description
The analog portion of the HI7188 consists of a 8 to 1 fully
differential Multiplexer, Programmable Gain Instrumentation
amplifier (PGIA) and a 4th order Sigma-Delta modulator.
Please refer to the simplified analog block diagram in Figure 8.
Analog Inputs
The analog inputs on the HI7188 are fully differential inputs
with programmable gain capabilities. The inputs accept both
unipolar and bipolar input signals and gains of 1, 2, 4 or 8.
The gain for any given physical channel is independent of
the gain of other physical channels. The gain is programmed
via the Channel Conguration Register (CCR).
The input impedance of the HI7188 is dependent upon the
modulator input sampling capacitors which varies with the
selected PGIA gain. Table 2 shows the sampling capacitors
and input impedances for the different gain settings of the
HI7188. Note that this table is valid only for a 3.6864MHz
master clock. If the input clock frequency is changed then
the input impedance will change accordingly. The equation
used to calculate the input impedance is
(RESET) INITIAL SYSTEM START
APPLY A ZERO SCALE INPUT
PROGRAM THE SYSTEM LEVEL
INFORMATION IN THE
CONTROL REGISTER (CR)
TO EACH OF THE CHANNELS
PROGRAM THE CHANNEL LEVEL
INFORMATION IN THE
CHANNEL CONFIGURATION
REGISTERS (CCR)
APPLY A POSITIVE FULL SCALE INPUT
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
POSITIVE FULL SCALE
TO EACH CHANNEL
CALIBRATION MODE
APPLY A NEGATIVE FULL SCALE
REPROGRAM THE CCR
TO PLACE EACH CHANNEL IN
NEGATIVE FULL SCALE
INPUT TO EACH CHANNEL
CALIBRATION MODE
CA OUTPUT
INTERRUPT ACTIVE?
YES
NO
CA OUTPUT
INTERRUPT ACTIVE?
YES
NO
CA OUTPUT
INTERRUPT ACTIVE?
YES
NO
CONNECT DESIRED ANALOG INPUT,
READ DATA RAM VIA
SERIAL INTERFACE
RECALIBRATION REQUIRED?
NO
YES
AND PLACE EACH CHANNEL
IN OFFSET CALIBRATION MODE
EOS OUTPUT
INTERRUPT ACTIVE?
NO
YES
FIGURE 7. SYSTEM USAGE FLOWCHART
4TH
ORDER
MODULATOR
CONVERSION
CONTROL
∑
VIN1H
VIN2H
VIN3H
VIN4H
VIN5H
VIN6H
VIN7H
VIN8H
VIN1L
VIN2L
VIN3L
VIN4L
VIN5L
VIN6L
VIN7L
VIN8L
PGIA
VRHI VRLO
VCM
PHYSICAL
CHANNELS
DIGITAL
SECTION
REFERENCE INPUTS
FIGURE 8. ANALOG BLOCK DIAGRAM
ZIN = 1/(CS x FS)
HI7188
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