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參數(shù)資料
| 型號： | HI7188IN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV A/D 16BIT 8:1 MUX 44-MQFP |
| 標準包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 240 |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個差分，單極；8 個差分，雙極 |
5
Pin Descriptions
44 LEAD
MQFP
PIN NAME
PIN DESCRIPTION
41
MODE
Mode input. Used to select between Synchronous Self Clocking (MODE = 1) or Synchronous External Clocking
(MODE = 0) for the Serial Port.
42
SCLK
Serial interface clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the falling
edge.
43
SDO
Serial Data Out. Serial data is read from this line when using a 3-wire serial protocol such as the Motorola Serial
Peripheral Interface.
44
SDIO
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
1
OSC1
Oscillator clock input for the device. A crystal connected between OSC1 and OSC2 will provide a clock to the
device, or an external oscillator can drive OSC1. The oscillator frequency should be 3.6864MHz to maintain Line
Noise Rejection.
2
OSC2
Used to connect a crystal source between OSC1 and OSC2. Leave open otherwise.
3, 30
DVDD
Positive Digital supply (+5V).
4, 29, 39
DGND
Digital supply ground.
5, 6, 27, 28
AVSS
Negative analog power supply (-5V).
7VINL1
Analog input low for Channel 1.
8VINH1
Analog input high for Channel 1.
9VINL2
Analog input low for Channel 2.
10
VINH2
Analog input high for Channel 2.
11
VINL3
Analog input low for Channel 3.
12
VINH3
Analog input high for Channel 3.
13
VINL4
Analog input low for Channel 4.
14
VINH4
Analog input high for Channel 4.
15
VINL5
Analog input low for Channel 5.
16
VINH5
Analog input high for Channel 5.
17
VINL6
Analog input low for Channel 6.
18
VINH6
Analog input high for Channel 6.
19
VINL7
Analog input low for Channel 7.
20
VINH7
Analog input high for Channel 7.
21
VINL8
Analog input low for Channel 8.
22
VINH8
Analog input high for Channel 8.
23
VCM
Common mode voltage. Must be tied to the mid point of AVDD and AVSS.
24
VRLO
External reference input. Should be negative referenced to VRHI.
25
VRHI
External reference input. Should be positive referenced to VRLO.
26
AVDD
Positive analog power supply (+5V).
31
RST
Active low Reset pin. Used to initialize modulator, lter, RAMs, registers and state machines.
32
CA
Calibration active output. Indicates that at least one active channel is in a calibration mode.
33
MXC
Multiplexer control output. Indicates that the conversion for the active channel is complete.
34
A0
Logical channel count output (LSB).
35
A1
Logical channel count output.
36
A2
Logical channel count output (MSB).
37
EOS
End of scan output. Signals the end of a channel scan (all active channels have been converted) and data is
available to be read. Remains low until data RAM is read.
38
RSTI/O
I/O reset (active low) input. Resets serial interface state machine only.
40
CS
Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and SDIO pins are
three-state.
HI7188
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