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參數(shù)資料
| 型號： | HI7188IN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV A/D 16BIT 8:1 MUX 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 240 |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個差分，單極；8 個差分，雙極 |
13
It is recommended that VCM be tied to analog ground when
operating off of AVDD = +5V and AVSS = -5V supplies. VCM
also determines the headroom at the upper and lower ends
of the power supplies which is limited by the common mode
input range where the internal operational ampliers remain
in the linear, high gain region of operation.
Sigma Delta Modulator
The sigma delta modulator is a fourth order modulator which
converts the differential analog signal into a series of one bit
outputs. The 1’s density of this data stream provides a digital
representation of the analog input. Figure 10 shows a
simplied block diagram of the analog modulator front end of
a Sigma-Delta A/D Converter. The input signal VIN comes
into a summing junction (the PGIA in this case) where the
previous modulator output is subtracted from it. The resulting
signal is then integrated and the output of the integrator goes
into the comparator. The output of the comparator is then fed
back via a one bit DAC to the summing junction. The
feedback loop forces the average of the fed back signal to be
equal to the input signal VIN.
Digital Section Description
A block diagram of the digital section of the HI7188 is shown
in Figure 11. This section includes an integrating lter,
averaging lters, calibration logic registers, output data RAM,
digital serial interface and a clock generator.
Integrating Filters
The integrating lter receives a stream of 1s and 0s from the
modulator at a rate of 614kHz. The 1’s density of this data
stream provides a digital representation of the analog input
signal. The integrating lter provides the low pass function
with a cutoff of 2kHz. The Integrating Filter works in concert
with the modulator and is controlled by the same clock and
reset signals. The lter integrates 201 1-bit samples from the
modulator for a valid “conversion” to be completed. At that
time the data is transferred to the Line Noise Rejection
(LNR) Filters or straight to calibration if LNR is not selected.
Line Noise Rejection
The line noise rejection section is used to eliminate a periodic
sine wave signal of either 50Hz or 60Hz line frequencies.
To understand the functionality of the HI7188 line noise
rejection (LNR), it is useful to discuss the method utilized by
a generic integrating analog to digital converter (ADC). This
ADC uses an external summing/integrating capacitor to sum
the line noise on a capacitor over one line noise cycle. The
cycle period is 16.67ms and 20ms for 60Hz and 50Hz
respectively. The ADC output is then the desired input with
the line noise summed to zero with a conversion rate equal
to the line noise frequency.
The HI7188 has the ability to do the same function as the
Integrating ADC but samples the input four times during the
line cycle (see Figure 12). For this discussion, the desired
analog input signal will be zero. The HI7188 accomplishes this
by instituting a four quadrant, four point running average
system. The microsequencer samples all eight inputs at
exactly the same point in time and for the exact amount of
time for each of the four quadrants of a single line cycle and
stores them separately. These four samples are then
summed, on a per channels basis, which results in the same
answer of the line synchronous noise as with the Integrating
ADC.
PGIA
INTEGRATOR
COMPARATOR
VRHI
VRLO
DAC
VIN
+
-
+
-
∫
FIGURE 10. SIMPLE MODULATOR BLOCK DIAGRAM
HI7188
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HI7188IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC 7188 DIP40 制造商:Harris Corporation 功能描述: |
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