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參數(shù)資料
| 型號： | HI7188IN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV A/D 16BIT 8:1 MUX 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 240 |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個差分，單極；8 個差分，雙極 |
6
Absolute Maximum Ratings
Thermal Information
Supply Voltage
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS to AVDD
Digital Input, Output and I/O Pins . . . . . . . . . . . . . . DGND to DVDD
ESD Tolerance (No Damage)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE:
1.
θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specications
AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND, VCM = AGND, PGIA Gain = 1,
OSCIN = 3.6864MHz, Bipolar Input Range Selected
PARAMETER
TEST CONDITION
-40oC TO 85oC
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
Dependent on Gain (Note 2)
-
16
Bits
Integral Non-Linearity, INL
FS = 25Hz, +FS, +MS, 0, -MS, -FS
End Point Line Method (Notes 3, 5, 6)
-
±0.0015
±0.0045
%FS
Differential Non-Linearity
(Note 2)
No Missing Codes to 16-Bits
-
Offset Error, VOS (Calibrated)
VINHI = VINLO (Notes 3, 4)
-
±0.0015
-
%FS
Full Scale Error, FSE (Calibrated)
VINHI - VINLO = +2.5V (Notes 3, 4)
-
±0.0015
-
%FS
Gain Error (Calibrated)
Slope = +Full Scale - (-Full Scale)
(Notes 3, 4)
-
±0.0015
-
%FS
Noise, VN(P-P)
-
1/4
-
LSB
Common Mode Rejection Ratio,
CMRR
VCM = 0V (Note 5) Delta VCM = ±3V
-
-75
-
dB
Off Channel Isolation
(Note 2)
-120
-
dB
ANALOG INPUT
Common Mode Input Range, VCM
(Note 2)
AVSS
-AVDD
-
Input Leakage Current, IIN
VIN = AVDD (Note 3)
-
1.0
nA
Input Capacitance, CIN
(Note 2) See Table 2
-
4.0
-
pF
DIGITAL INPUTS
Input Logic High Voltage, VIH
2.0
-
V
Input Logic Low Voltage, VIL
-
0.8
V
Input Logic Current, II
VIN = 0V, +5V
-
1.0
10
A
Input Capacitance, CIN
VIN = 0V (Note 2)
-
5.0
-
pF
DIGITAL CMOS OUTPUTS
Output Logic High Voltage, VOH
IOUT = -100A (Note 7)
2.4
-
V
Output Logic Low Voltage, VOL
IOUT = 3.2mA (Note 7)
-
0.4
V
Output Three-State Leakage
Current, IOZ
VOUT = 0V, +5V (Note 7)
-
1
10
A
Digital Output Capacitance, COUT
(Note 2)
-
10
-
pF
HI7188
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