參數(shù)資料
型號(hào)： HDMP-1034
英文描述： 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
中文描述： 1.4 GBd接收芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd接收器）
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 346K
代理商： HDMP-1034
20
HDMP-1034 (Rx) Pin Definition (continued)
Pass System
RXDSLIP
6
O-TTL
Rx Word Slip:
This output is asserted whenever the phase of the
parallel word relative to the reference clock has exceeded the
range of the internal delay, which results in a slippage of one
word. See discussion of PASS system on page 7.
Shift Input:
This input controls the delay of the parallel bits to
be clocked out by REFCLK when PASSENB=1. In a single Rx
configuration, SHFIN is connected to SHFOUT. In a multiple Rx
configuration, all SHFIN are connected to the master’s SHFOUT.
Shift Output:
This output, normally connected to SHFIN, is
generated based on the relative phase between REFCLK and
the internal parallel output bits.
Shift Request Input:
In a daisy chain configuration, this input
allows a shift request to be propagated to the master. SRQIN is
connected to the SRQOUT of the previous Rx in a multi-receiver
configuration.
Shift Request Output:
In a daisy chain configuration, this output
is connected to the SRQIN input of the next receiver. SRQOUT
goes high when a SRQIN=1 or when the relative phase between
the REFCLK and the internal parallel bits requires a shift.
SHFIN
13
I-TTL
SHFOUT
14
O-TTL
SRQIN
34
I-TTL
SRQOUT
15
O-TTL
Test Mode/No Connect Pins
TSTCLK
12
I-TTL
External Serial Rate Clock Input:
When RXDIV1/0 = 1/1, this input
is used in place of the normal VCO signal, effectively disabling
the PLL and allowing the user to provide an external serial clock
for testing. Pin is normally tied to V
CC
_TTL.
Reset:
When this active low input is asserted the word alignment
is reset. Upon release (low to high) the normal word alignment
process is reinstated. Pin used for test purposes and is normally
tied to V
CC
_TTL.
Word Sync Disable:
When high, disables resynchronization to
word edge upon errors encountered in the C-field of the incoming
encoded word. Pin used for test purposes and is normally tied low.
No Connect:
These pins should be left unconnected.
#RESET
35
I-TTL
WSYNCDSB
36
I-TTL
NC
21
27
相關(guān)PDF資料
PDF描述
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HDMP-1514 Fibre Channel Receiver Chipset(光纖通道接收芯片)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1034A 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set
HDMP-1512 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset
HDMP-1514 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset
HDMP1526 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
HDMP-1526 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip
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