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參數(shù)資料
| 型號(hào)： | HDMP-1034 |
| 英文描述： | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| 中文描述： | 1.4 GBd接收芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd接收器） |
| 文件頁(yè)數(shù)： | 10/32頁(yè) |
| 文件大?。?/td> | 346K |
| 代理商： | HDMP-1034 |
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Figure 5. HDMP-1032 (Tx) Timing Diagram.
HDMP-1032 (Tx) Timing Characteristics
Tc = –20
°
C to +85
°
C, V
CC
= 3.15V to 3.45V
Symbol
Parameter
t
s
Setup Time, for TX[0-15], TXDATA, TXCNTL and
TXFLAG Relative to Rising Edge of TXCLK.
t
h
Hold Time, for TX[0-15], TXDATA, TXCNTL and
TXFLAG Relative to Rising Edge of TXCLK.
Unit
nsec
Min.
2.5
Typ.
Max.
nsec
2.5
HDMP-1032 (Tx) Timing
The Tx timing diagram is shown
in Figure 5. Under normal opera-
tions, the Tx PLL locks an inter-
nally generated clock to the
incoming TXCLK at which time
LOCKED is set high. The incom-
ing data, TX[0-15], TXDATA,
TXCNTL, and TXFLAG are
latched by this internal clock. The
data must be valid for t
s
before it is sampled and remain
valid for a time t
h
after it is
sampled.
The setup and hold time param-
eters, t
s
and t
h
, are referenced to
the rising edge of TXCLK.
The start of a word, bit TX[0],
in the high speed serial output
occurs after a delay of t
d
after
the rising edge of the TXCLK.
The typical value of t
d
is
approximately one clock cycle.
t
s
t
h
t
d
W-FIELD
C-FIELD
TXCLK
TX[0-15]
TXDATA
TXCNTL
TXFLAG
HSOUT
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| HDMP-1034A | 制造商:HP 制造商全稱(chēng):Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
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| HDMP-1526 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Fibre Channel Transceiver Chip |
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