參數(shù)資料
型號: HDMP-1034
英文描述: 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
中文描述: 1.4 GBd接收芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd接收器)
文件頁數(shù): 11/32頁
文件大?。?/td> 346K
代理商: HDMP-1034
11
Figure 6. HDMP-1034 (Rx) Timing Diagram.
HDMP-1034 (Rx) Timing Characteristics
Tc = –20
°
C to +85
°
C, V
CC
= 3.15V to 3.45V. Typical values are at Tc = 25
°
C, V
CC
= 3.3V
Symbol
Parameter
t
d
Synchronous Output Delay referenced to the falling
edge of RXCLK1, PASS System Disabled (PASSENB=0).
t
dp
Synchronous Output Delay referenced to the rising
edge of REFCLK, PASS System Enabled (PASSENB=1).
t
sk
Allowable skew between HSIN and REFCLK before
PASS system resets, PASSENB=1.
Unit
nsec
Min.
0
Typ.
2.0
Max.
3.5
nsec
6.0
6.6
8.0
nsec
20% word
period
-0.4 nsec
HDMP-1034 (Rx) Timing
The Rx timing diagram when
RXREADY=1 is shown in Figure
6. The serial data stream is
deserialized into a parallel word
at 1/20 the serial baud rate.
When the PASS system is dis-
abled (PASSENB=0), there is a
latency delay of two words from
the input of the first serial bit of a
word to the parallel outputs. The
parallel outputs, RX[0-15],
RXFLAG, RXREADY, RXERROR,
RXDATA, RXCNTL and RXDSLIP
are clocked out with the falling
edge of RXCLK1 and appear after
a delay of t
d
. RXCLK1 and its
complement RXCLK0 are both
50% duty cycle clocks.
When the PASS system is enabled
(PASSENB=1), the timing of the
parallel word is adjusted auto-
matically
±
30% of the word pe-
riod so that it can be clocked out
with the rising edge of REFCLK
and appear after a delay of t
dp
.
C
WORD 1
W
C
WORD 2
W
C
WORD 3
W
C
WORD 4
W
HSIN
RXCLK1
RXCLK0
REFCLK
t
dp
t
d
RX[0]
BIT 0
NOTE: W = 16 BIT WORD FIELD,
C = 4 BIT CODE FIELD
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