參數(shù)資料
型號(hào)： HB52R1289E22
廠商： Hitachi,Ltd.
英文描述： 1 GB Registered SDRAM DIMM(1GB 寄存同步DRAM DIMM)
中文描述： 1 GB的注冊(cè)SDRAM的內(nèi)存（1GB的寄存同步的DRAM內(nèi)存）
文件頁(yè)數(shù)： 18/21頁(yè)
文件大?。?/td> 98K
代理商： HB52R1289E22
HB52R1289E22-A6B/B6B
18
Notes:
1.I
RCD
to I
RRD
are recommended value.
2.Be valid [DSEL] or [NOP] at next command of self refresh exit.
3.Except [DSEL] and [NOP]
Pin Functions
CK0 to CK3 (input pin):
CK is the master clock input to this pin. The other input signals are referred at
CK rising edge.
S0 to S3 (input pin):
When S is Low, the command input cycle becomes valid. When S is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins):
Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the com-
bination of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins):
Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11 level
at the read or write command cycle CK rising edge. And this column address becomes burst access start ad-
dress. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/
BA1 (BA) is precharged.
BA0/BA1 (input pin):
BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0,
bank 1, bank 2 and bank 3. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is High and BA1 is
Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
CKE0 (input pin):
This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and
clock suspend modes.
DQMB0 to DQMB7 (input pins):
Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins):
Data is input to and output from these pins.
V
CC
(power supply pins):
3.3 V is applied.
V
SS
(power supply pins):
Ground is connected.
Parameter
Frequency (MHz)
HB52R1289E22
-A6B/B6B
t
CK
(ns)
Burst stop to output high impedance
(CE latency = 3)
(CE latency = 4)
Burst stop to write data ignore
HITA-
CHI-
Symbol
I
BSH
PC100
Symbol 10
Notes
3
I
BSH
I
BSW
4
1
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