參數(shù)資料
型號(hào): HB52F168EN
廠商: Hitachi,Ltd.
英文描述: 64 MB Unbuffered SDRAM DIMM(64 MB 未緩沖同步DRAM DIMM)
中文描述: 64 MB的無(wú)緩沖SDRAM的內(nèi)存(64 MB的未緩沖同步的DRAM內(nèi)存)
文件頁(yè)數(shù): 29/71頁(yè)
文件大小: 906K
代理商: HB52F168EN
HB52F88EM-75F, HB52F89EM-75F, HB52F168EN-75F, HB52F169EN-
29
AC Characteristics (Ta = 0 to 65
°
C, V
CC
= 3.3 V
±
0.3 V, V
SS
= 0 V)
Notes:
1.AC measurement assumes t
T
= 1 ns. Reference level for timing of input signals is 1.5 V.
2.Access time is measured at 1.5 V. Load condition is C
L
= 50 pF.
3.t
LZ
(max) defines the time at which the outputs achieves the low impedance state.
4.t
HZ
(max) defines the time at which the outputs achieves the high impedance state.
5.t
CES
defines CKE setup time to CK rising edge except power down exit command.
HB52F88EM/89EM/
168EN/169EN-75F
PC133
CE latency = 3
PC100
CE latency = 2
Parameter
System clock cycle time
CK high pulse width
CK low pulse width
Access time from CK
Data-out hold time
CK to Data-out low impedance
CK to Data-out high impedance
Data-in setup time
Data in hold time
Address setup time
Address hold time
CKE setup time
CKE setup time for power down exit t
CESP
CKE hold time
Command setup time
Command hold time
Ref/Active to Ref/Active command
period
Active to precharge command
period
Active command to column
command (same bank)
Precharge to active command
period
Write recovery or data-in to
precharge lead time
Active (a) to Active (b) command
period
Transition time (rise to fall)
Refresh period
HITA-
CHI-
Symbol
t
CK
t
CKH
t
CKL
t
AC
t
OH
t
LZ
t
HZ
t
DS
t
DH
t
AS
t
AH
t
CES
PC100
Sym-
bol
Tclk
Tch
Tcl
Tac
Toh
Min
7.5
2.5
2.5
2.7
2
1.5
0.8
1.5
0.8
1.5
1.5
0.8
1.5
0.8
67.5
Max
5.4
5.4
Min
10
3
3
3
2
2
1
2
1
2
2
1
2
1
70
Max
6
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
s
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1, 5
1
1
1
1
1
Tsi
Thi
Tsi
Thi
Tsi
Tpde
Thi
Tsi
Thi
Trc
t
CEH
t
CS
t
CH
t
RC
t
RAS
Tras
45
120000
50
120000
ns
1
t
RCD
Trcd
20
20
ns
1
t
RP
Trp
20
20
ns
1
t
DPL
Tdpl
10
10
ns
1
t
RRD
Trrd
15
20
ns
1
t
T
t
REF
1
5
64
1
5
64
ns
ms
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