參數(shù)資料
型號(hào)： GS9092
廠(chǎng)商： Gennum Corporation
英文描述： GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述： GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁(yè)數(shù)： 6/58頁(yè)
文件大小： 608K
代理商： GS9092
GS9092 Data Sheet
28202 - 2
September 2005
6 of 58
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
1
LF-
Analog
Input
Loop filter component connection. Connect to LF+ through a capacitor.
See
Typical Application Circuit on page 55
.
2
PLL_GND
Analog
Input
Power
Ground connection for phase-locked loop. Connect to GND.
3
PLL_VDD
Analog
Input
Power
Power supply connection for phase-locked loop. Connect to +1.8V DC.
4
CD_VDD
Analog
Input
Power
Power supply connection for serial digital cable driver. Connect to
+1.8V DC
5, 6
SDO, SDO
Analog
Output
Serial digital differential output pair.
NOTE: these output signals will be forced into a mute state if RESET is
LOW.
7
CD_GND
Analog
Input
Power
Ground connection for serial digital cable driver. Connect to GND.
8
NC
–
–
No connect.
9
RSET
Analog
Input
An external 1% resistor connected between this input and CD_VDD is
used to set the SDO / SDO output amplitude.
10
VBG
Analog
Input
Bandgap filter capacitor. Connect as shown in the
Typical Application
Circuit on page 55
11
SDO_EN
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible
Used to enable or disable the serial digital output.
When set LOW by the application layer, the serial digital output signals
SDO and SDO are muted.
When set HIGH by the application layer, the serial digital output signals
are enabled.
SDO and SDO outputs will also be high impedance when the RESET
pin is LOW.
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