- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385345 > GS9092 (Gennum Corporation) GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI PDF資料下載
參數(shù)資料
| 型號： | GS9092 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| 中文描述： | GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi) |
| 文件頁數(shù)： | 23/58頁 |
| 文件大?。?/td> | 608K |
| 代理商： | GS9092 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
GS9092 Data Sheet
28202 - 2
September 2005
23 of 58
3.3.1 Video Mode
The internal FIFO is in video mode under the following conditions:
the FIFO_EN and IOPROC_EN pins are set HIGH,
the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register (
Table 3-4
) are
configured to 00b,
the DETECT_TRS pin is set LOW; and
TRS insertion, EDH correction/insertion, illegal code re-mapping, and SMPTE
packet insertion are all disabled (i.e. bits 0, 2, 3, and 4 of the
IOPROC_DISABLE register are set HIGH).
NOTE: The FIFO will still enter video mode if any of bits 0, 2, 3, or 4 of the
IOPROC_DISABLE register are LOW; however, the output video data will contain
errors.
By default, the FIFO_MODE[1:0] bits are set to 00b by the device whenever the
SMPTE_BYPASS pin is set HIGH and the DVB_ASI and DETECT_TRS pins are
set LOW.
In video mode, the H, V, and F pins become input signals that must be supplied by
the user.
Figure 3-2
shows the input and output signals of the FIFO when it is configured for
video mode.
Figure 3-2: FIFO in Video Mode
When operating in video mode, the GS9092 will read data sequentially from the
FIFO, starting with the first active pixel in location zero of the memory. In this mode,
it is possible to use the FIFO for clock phase interchange and data delay.
The device will ensure read-side synchronization is maintained, according to the
supplied PCLK and supplied H, V, and F timing information.
Full write-control of the FIFO is made available to the application interface such
that data is clocked into the FIFO on the rising edge of the externally provided
WR_CLK. The FIFO write pointer will be reset to position zero of the memory when
there is a HIGH-to-LOW transition at the WR_RESET pin.
WR_CLK
FIFO
(Video Mode)
RD_CLK (PCLK)
10-bit Video Data
10-bit Video Data
WR_RESET
RD_RESET
(supplied H timing)
Application Interface
Internal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9092-CNE3 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GSC9620 | P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| GSD2004S-V-GS08 | DIODE 0.225 A, 300 V, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB, ROHS COMPLIANT, PLASTIC PACKAGE-3, Signal Diode |
| GSD2004S-V-GS18 | DIODE 0.225 A, 300 V, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB, ROHS COMPLIANT, PLASTIC PACKAGE-3, Signal Diode |
| GSD2004W-V-GS18 | DIODE 0.225 A, 300 V, SILICON, SIGNAL DIODE, ROHS COMPLIANT, PLASTIC PACKAGE-2, Signal Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9092A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092A_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092ACNE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS9092ACNTE3 | 制造商:Semtech Corporation 功能描述:270Mb/s Transmitter for SDI & ASI |
| GS9092CNE3 | 制造商:Gennum Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。