參數(shù)資料
型號(hào)： GS9092
廠商： Gennum Corporation
英文描述： GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述： GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁(yè)數(shù)： 48/58頁(yè)
文件大?。?/td> 608K
代理商： GS9092
GS9092 Data Sheet
28202 - 2
September 2005
48 of 58
3.12 GS9092 Low Latency Mode
When the IOPROC_EN pin is set LOW, the GS9092 will enter a low-latency mode
such that the serial digital data will be output with the minimum PCLK latency
possible. The FIFO and all processing blocks except the SMPTE scrambling block
will be bypassed when SMPTE_BYPASS is HIGH.
Low-latency mode will also be selected when SMPTE_BYPASS is set LOW,
regardless of the setting of the IOPROC_EN signal (see
Table 3-12
).
In DVB-ASI mode (
DVB-ASI Mode on page 33
), the device will have a higher
latency then low-latency mode, although this latency will be less than SMPTE
mode (
SMPTE Mode on page 32
).
Table 3-11: STAT [2:0] Output Default Configuration
Device Configuration
IO_CONFIG
Register
I/O
Function
Default
IO_CONFIG
Setting
SMPTE Functionality
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
FIFO: Video Mode or Ancillary
Data Insertion Mode
STAT0_CONFIG
I/O
H
000b
STAT1_CONFIG
I/O
V
001b
STAT2_CONFIG
I/O
F
010b
DVB-ASI
DVB_ASI = HIGH
FIFO: DVB-ASI Mode
STAT0_CONFIG
Output
FIFO_FULL
110b
STAT1_CONFIG
Output
FIFO_EMPTY
111b
STAT2_CONFIG
Output
High Z
000b
Data-Through
SMPTE_BYPASS = LOW
DVB_ASI = LOW
STAT0_CONFIG
Output
High Z
000b
STAT1_CONFIG
Output
High Z
000b
STAT2_CONFIG
Output
High Z
000b
Table 3-12: Pin Settings in Low-latency Mode
IOPROC_EN Setting
SMPTE_BYPASS
Setting
Latency
(PCLK Cycles)
LOW
LOW
9
HIGH
LOW
10
LOW
HIGH
8
HIGH
HIGH
21
相關(guān)PDF資料
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