參數(shù)資料
型號： GS9092
廠商： Gennum Corporation
英文描述： GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述： GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁數(shù)： 50/58頁
文件大?。?/td> 608K
代理商： GS9092
GS9092 Data Sheet
28202 - 2
September 2005
50 of 58
3.13.1 Command Word Description
The command word consists of a 16-bit word transmitted MSB first and contains a
read/write bit, an Auto-Increment bit and a 12-bit address.
Figure 3-11
shows the
command word format and bit configurations.
Command words are clocked into the GS9092 on the rising edge of the serial clock
SCLK, which operates in a burst fashion.
When the Auto-Increment bit is set LOW, each command word must be followed
by only one data word to ensure proper operation. If the Auto-Increment bit is set
HIGH, the following data word will be written into the address specified in the
command word, and subsequent data words will be written into incremental
addresses from the previous data word. This facilitates multiple address writes
without sending a command word for each data word.
Auto-Increment may be used for both read and write access.
3.13.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown in
Figure 3-13
and
Figure 3-14
respectively. The timing parameters are defined in
Table 3-13
.
When several devices are connected to the GSPI chain, only one CS must be
asserted during a read sequence.
During the write sequence, all command and following data words input at the
SDIN pin are output at the SDOUT pin as is. Where several devices are connected
to the GSPI chain, data can be written simultaneously to all the devices that have
CS set LOW.
Table 3-13: GSPI Timing Parameters
Parameter
Definition
Specification
t
0
The minimum duration of time chip select, CS, must be
LOW before the first SCLK rising edge.
1.5 ns
t
1
The minimum SCLK period.
18.5 ns
t
2
Duty cycle tolerated by SCLK.
40% to 60%
t
3
Minimum input setup time.
1.5 ns
t
4
Write Cycle: the minimum duration of time between the
last SCLK command (or data word if the Auto-Increment
bit is HIGH) and the first SCLK of the data word.
37.1 ns
t
5
Read Cycle: the minimum duration of time between the
last SCLK command (or data word if the Auto-Increment
bit is HIGH) and the first SCLK of the data word.
148.4 ns
t
5
Read Cycle - ANC_DATA_RDBACK bit HIGH when FIFO
is in ancillary insertion mode (see
Ancillary Data Insertion
on page 29
): the minimum duration of time between the
last SCLK command (or data word if the Auto-Increment
bit is HIGH) and the first SCLK of the data word.
222.6 ns
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