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| 型號(hào)： | GMS30C7201 |
| 英文描述： | 32-Bit RISC Microprocessor(32位 RISC 微處理器) |
| 中文描述： | 32位RISC微處理器（32位的RISC微處理器） |
| 文件頁(yè)數(shù)： | 203/354頁(yè) |
| 文件大小： | 1639K |
| 代理商： | GMS30C7201 |
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Fast AMBA Peripherals
12-47
GMS30C7201 Data Sheet
CPU and DMA Register Access Sizes
Bit positioning, byte ordering, and addressing of the FIr is describes in terms of little
endian ordering. All FIr control and status registers are 8 bits wide and are located in
the least significant byte of individual words. Data transfers are up to 32 bits wide. If the
DMA controller is used to service the transmit and/or receive buffers, the user must
ensure the DMA is properly configured to perform single word-wide accesses.
DMA burst mode access is not supported.
FIr Register Definitions
The Fir uses the control and data registers described in
12.3 Medium and Fast
Infrared Module
on page 12-17. In addition there are two status registers specific to
the FIr
The status registers contain bits which signal CRC, overrun, underrun, framing, and
receiver abort errors as well as the transmit buffer service request, receive buffer
service request, and end of frame conditions. Each of these hardware detected events
signal an interrupt request to the interrupt controller. The status registers also contain
flags for transmitter busy, receiver synchronized, receive buffer not empty, and transmit
buffer not full (no interrupt generated).
The status registers contain bits which signal CRC, overrun, underrun, framing, and
receiver abort errors as well as the transmit buffer service request, receive buffer
service request, and end of frame conditions. Each of these hardware detected events
signal an interrupt request to the interrupt controller. The status registers also contains
flags for transmitter busy, receiver synchronized, receive buffer not empty, and transmit
buffer not full (no interrupt generated).
12.9.1 FIr Status Register 0
FIr status register 0 (FISR0) contains bits which signal the transmit buffer service
request, receive buffer service request, receiver abort, transmit buffer underrun,
framing error, and the end/error in receive buffer condition. Each of these hardware
detected events signal an interrupt request to the interrupt controller.
Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once
the bit is cleared, the interrupt is cleared. Read/write bits are called status bits, read-
only bits are called flags. Status bits are referred to as
“
sticky
”
(once set by hardware,
must be cleared by software). Writing a one to a sticky status bit clears it, writing a zero
has no effect. Read-only flags are set and cleared by hardware, writes have no effect.
Additionally some bits which cause interrupts have corresponding mask bits in the
control registers and are indicated in the section headings below.
End/Error in buffer Status (EIF) (read/write, non-maskable interrupt)
The end/error in buffer status bit (EIF) is set when any tag bits (32 through 36) are set
in the receive buffer. When EIF is set an interrupt is signalled and DMA requests to
empty the receive buffer are disabled until EIF is cleared
Transmit Underrun Status (TUR) (read/write, maskable interrupt)
The transmit underrun status bit (TUR) is set when the transmit logic attempts to fetch
data from the transmit buffer after it has been completely emptied. When an underrun
occurs, the transmitter takes one of two actions. When the transmit underrun select bit
is clear (TUS=0) the transmitter ends the frame by shifting out the CRC which is
calculated continuously on outgoing data, followed by a stop flag and SIP pulse. When
TUS=1, the transmitter is forced to transmit an abort and continues to transmit symbols
containing all zeros (0000) until valid data is again available within the buffer. Once data
resides within the bottom entry of the transmit buffer, a new data frame is initiated by
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