
Fast AMBA Peripherals
12-18
GMS30C7201 Data Sheet
12.3.3 IrEnable Register
The register IrEnable selects which of the three Ir sub-modules (SIr, MIr and FIr) is used
to operate the IrDA interface. Only one of the three may be active at any one time. The
reset value for this register is zero which disables all three encoder/decoder modules.
The bottom two bits of this register select the encoder decoder module according to the
tabulated values listed below.
This register may also be used to enable a hardware loopback mode for the sub-
module selected.
Loop Back Mode (LBM)
The loop back mode (LBM) bit is used to enable and disable the ability of the Ir transmit
output to be fed back into the receive logic for diagnostic purposes. When LBM=0, the
selected Ir module operates normally. The transmit and receive data paths are
independent and communicate via their respective pins. When LBM=1, the output of
the transmit serial shifter is directly connected to the input of the receive serial shifter
internally.
Note that even though the IrDA standard only permits half-duplex operation, this
implementation does not restrict the user from transmitting and receiving data at the
same time; both are fully independent units.
Transmitter Disabled Bits (FD/MD)
Two read-only status bits are provided within this register: FD and MD. When set these
bits indicate that the FIr/MIr transmit module has completed transmission of the current
frame and that it is safe to disable the module using bits EN1 and EN0. This feature
simplifies clean switching between IrDA formats.
IrEnable Register:
Figure 12-2: Ir Enable register bits
shows the register bits in Ir Enable.
Figure 12-2: Ir Enable register bits
IrEnable
Value
(EN1,EN0)
Encoder
Selected
Data Rate (Mbit/s)
Modulation
Scheme
Data
Interface
00
None
-
-
-
01
SIr
0
–
0.1152
NRZ + HP-SIR
Serial port
10
MIr
0.576 or 1.152
NRZ + HDLC
Fast APB
11
FIr
4.0
4PPM
Fast APB
Table 12-24: Ir Interface Mode Selection
Address: 0h80011000
IrEnable
Read/Write
Bit
7
6
5
4
3
2
1
0
Res. Res. Res. FD
MD
LBM EN1 EN0
Reset
0
0
0
1
1
0
0
0