參數(shù)資料
型號(hào): GM5060
廠商: Electronic Theatre Controls, Inc.
英文描述: GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述: 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁(yè)數(shù): 70/85頁(yè)
文件大?。?/td> 1375K
代理商: GM5060
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
62
4
4
.
.
1
1
7
7
B
B
o
o
o
o
t
t
s
s
t
t
r
r
a
a
p
p
C
C
o
o
n
n
f
f
i
i
g
g
u
u
r
r
a
a
t
t
i
i
o
o
n
n
During hardware reset, the frame store address lines (FSADDR [13:0]) are configured as inputs.
On the de-assertion of reset (rising edge of RESETn), the value on the address lines is captured
by the gm5060. The designer should install a 10K pull-up resistor to indicate a ‘1’and connect to
ground to indicate a ‘0’. The captured values are latched into readable host registers. The value
on FSADDR [6:0] specifies the 2-wire host protocol device address.
Note:
All bootstrap pins must be connected to a known logic voltage and NOT be left floating.
Table 14. Bootstrap Signals
Shared With
Description
Name
I/O
ADDR(6:0)
I
FSADDR(6:0)
If using 2-wire protocol, this determines the chip address.
USER_BITS(4:0)
I
FSADDR(4:0)
If using 6-wire nibble protocol, these settings are available for reading from a
status register for any general-purpose user function. They are otherwise
unused by the IC.
Reserved
I
FSADDR5
If using 6-wire nibble protocol, bootstrap this bit to 0.
Reserved
I
FSADDR6
If using 6-wire nibble protocol, bootstrap this bit to 0.
HOST_PROTOCOL
I
FSADDR7
Selects the host interface protocol
0 = 2-wire protocol
1 = 6-wire (nibble) protocol (recommended)
USER_BITS(7:5)
I
FSADDR(10:8)
These settings are available for reading from a status register for any general-
purpose user function. They are otherwise unused by the IC
OCM_START
I
FSADDR11
Set to ‘0’
OCM_CLK
I
FSADDR13:12
Select over-sampling clock source for Host Interface and OCM.
00 = RCLK PLL / 2
10 = TCLK
00, 01 = EXTCLK
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