參數(shù)資料
型號(hào)： GM5060
廠商： Electronic Theatre Controls, Inc.
英文描述： GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述： 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁數(shù)： 17/85頁
文件大?。?/td> 1375K
代理商： GM5060
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
9
Name
I/O
Ball#
Description
DBGRN3
DBGRN2
DBGRN1
DBGRN0
DBBLU7
DBBLU6
DBBLU5
DBBLU4
DBBLU3
DBBLU2
DBBLU1
DBBLU0
A19
A20
B19
B20
C19
C20
D18
D19
D20
E18
E19
E20
O
Display output blue data (odd or right pixel).
[Tri-state output, programmable drive 0-24mA, not 5V-tolerant]
Table 7.
Description
Frame Store Interface Signals
Name
I/O
Ball#
FSCLK
O
T3
SDRAM clock. This signal is rising edge active.
[Tri-state output, Programmable Drive 0-24mA, not 5V-tolerant]
FSCKE
O
U1
SDRAM clock enable. This signal is active high.
[Tri-state output, 8mA drive, 5V-tolerant]
FSRAS
O
V1
SDRAM row address strobe. This signal is active low
[Tri-state output, 8mA drive, 5V-tolerant]
FSCAS
O
U3
SDRAM column address strobe. This signal is active low.
[Tri-state output, 8mA drive, 5V-tolerant]
FSWE
O
U2
SDRAM write enable. This signal is active low.
[Tri-state output, 8mA drive, 5V-tolerant]
FSDQM3
FSDQM2
FSDQM1
FSDQM0
O
W12
V12
Y8
W8
SDRAM data masks. Each bit enables one of four SDRAM byte “l(fā)anes”. This allows host OSD access
to the SDRAM to be byte oriented. This signal is active high.
Bit 0 enables FSDATA(7:0).
Bit 1 enables FSDATA(15:8).
Bit 2 enables FSDATA(23:16).
Bit 3 enables FSDATA(31:24).
[Tri-state output, 8mA drive, 5V-tolerant]
FSADDR13
FSADDR12
FSADDR11
FSADDR10
FSADDR9
FSADDR8
FSADDR7
FSADDR6
FSADDR5
FSADDR4
FSADDR3
FSADDR2
FSADDR1
FSADDR0
IO
V2
W1
Y1
W2
Y2
V3
W3
Y3
V4
W4
Y4
V5
W5
Y5
SDRAM multiplexed address bus.
FSADDR[13:0] are used for bootstrapping configuration. See Section 4.17.
[Bidirectional, 8mA drive output, 5V-tolerant]
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