參數(shù)資料
型號(hào)： GM5060
廠商： Electronic Theatre Controls, Inc.
英文描述： GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS
中文描述： 圖形處理芯片提供高品質(zhì)的圖像液晶顯示器
文件頁(yè)數(shù)： 14/85頁(yè)
文件大?。?/td> 1375K
代理商： GM5060
Genesis Microchip
gm5060 / gm5060-H Data Sheet
February 2002
C5060-DAT-01G
6
3. PIN LIST
I/O Legend: I
= Input
O
= Output
P
= Power
G
= Ground
Table 1.
ADC Signals
Name
I/O
Ball#
Description
REXT
I
B10
External termination resistor. A 1% 1K ohm resistor must be connected from this pin to AVDD_3.3
(3.3V analog power supply). This termination resistor determines current references for both the DVI
receiver block and Analog HSYNC Delay block for both DVI and analog configurations.
RED+
I
E1
Positive analog input for Red channel.
RED-
I
E2
Negative analog input for Red channel.
GREEN+
I
D2
Positive analog input for Green channel.
GREEN-
I
D1
Negative analog input for Green channel.
BLUE+
I
C1
Positive analog input for Blue channel.
BLUE-
I
C2
Negative analog input for Blue channel.
HSYNC
I
L2
ADC input horizontal sync or composite sync input.
[Input, schmitt trigger (400mV typical hysteresis), 5V-tolerant]
VSYNC
I
K1
ADC input vertical sync.
[Input, schmitt trigger (400mV typical hysteresis), 5V-tolerant]
Table 2.
Description
DVI Receiver Signals
Name
I/O
Ball#
REXT
I
B10
External termination resistor. A 1% 1K ohm resistor must be connected from this pin to AVDD_3.3
(3.3V analog power supply). This termination resistor determines current references for both the DVI
receiver block and Analog HSYNC Delay block for both DVI and analog configurations.
RX2+
I
C10
DVI input channel 2 positive component; RED data and embedded CTL3
RX2-
I
D10
DVI input channel 2 negative component; RED data and embedded CTL3
RX1+
I
C9
DVI input channel 1 positive component; GREEN data
RX1-
I
D9
DVI input channel 1 negative component; GREEN data
RX0+
I
C8
DVI input channel 0 positive component; BLUE data
RX0-
I
D8
DVI input channel 0 negative component; BLUE data
RXC+
I
C6
DVI input clock positive component
RXC-
I
D6
DVI input clock negative component
For the gm5060-H (HDCP-enabled), this pin is used for DDC Interface for DVI-HDCP
communication. This is SCL for slave-only DDC communication.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
DDC_SCL
I
N2
For the gm5060 (non-HDCP), this pin is an unused CMOS input that may be left unconnected.
However, it is preferred that this pin be connected to a known logic state.
For the gm5060-H (HDCP-enabled), this pin is used for DDC Interface for DVI-HDCP
communication. This is SDA for slave-only DDC communication.
[Bidirectional, 4mA drive output, Schmitt trigger input (400mV typical hysteresis), 5V-tolerant]
DDC_SDA
IO
N3
For the gm5060 (non-HDCP), this pin is an unused CMOS input that may be left unconnected.
However, it is preferred that this pin be connected to a known logic state.
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