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| 型號： | GC1012A-CQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DIGITAL TUNER CHIP |
| 中文描述： | 數(shù)字調(diào)諧器芯片 |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 186K |
| 代理商： | GC1012A-CQ |
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GRAYCHIP,INC.
- 24 -
FEBRUARY 18, 1998
GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
This document contains information which may be changed at any time without notice
5.8
LATENCY THROUGH THE GC1012A
Two latencies are of interest, the latency from a step function in to a step function out (midpoint), and the
latency from a step function until the end of the òringingó in the step function output (endpoint). These latencies are:
Another latency of interest is the delay from SS input to stable WS. The WS strobe becomes stable and is
low after 9 clocks, before 9 clocks the WS is unknown and may go high at any time. The delay until the first valid
high WS is a function of decimation. For decimate by 2 the delay from SS is 10 clocks, for 4 the delay is 12 clocks,
for 8 the delay is 16 clocks and for decimation ratios of 16, 32 and 64 the delay is 24 clocks. WS is high at clock 24
for all decimations.
Table 6: Latency
Output Mode
Midpoint
Endpoint
Values of D
(decimation)
Real
41 + 20D
41 + 40D
1, 2, 4, 8, 16 and 32
Complex
35 + 10D
35 + 20D
2, 4, 8, 16, 32 and 64
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