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| 型號： | GC1012A-CQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DIGITAL TUNER CHIP |
| 中文描述： | 數(shù)字調(diào)諧器芯片 |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 186K |
| 代理商： | GC1012A-CQ |
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GRAYCHIP,INC.
- 6 -
FEBRUARY 18, 1998
GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
This document contains information which may be changed at any time without notice
1.8
OUTPUT FORMATTING
The output format circuit allows the user to flip the output spectrum, to offset the spectrum by
one-fourth the Nyquist rate, to convert the complex output stream to a real one at twice the rate, to round
the samples to 10, 12, 14 or16 bits, and to multiplexes the I and Q samples together. These options are set
using control register 8.
A word strobe (
WS
) is generated as an output clock signal. The
WS
strobe is either one clock cycle
wide or is a 50% duty cycle clock. The polarity of
WS
is programmable.
The I and Q samples can be multiplexed together onto the I output pins by using the IQMUX mode.
The
IFLAG
output pin is used in this mode to identify when the I words are being output. The
WS
strobe
rate is doubled in this mode. The Q output pins are cleared in this mode.
Only the I output pins are used in the real mode. The Q pins are cleared. The output spectrum is
centered from 0 to F
O
/2 in the real mode. The spectrum is centered from -F
O
/2 to +F
O
/2 in the complex
mode. The OFFSET control allows the spectrum to be centered from 0 to F
O
.
The output format circuitry is synchronized by the
SS
input sync. This allows one to synchronize the
output timing of multiple GC1012A chips.
1.9
POWER DOWN AND KEEPALIVE MODES
Unused chips in a system can be powered down by setting the POWER_DOWN control bit in
register 9 (See Section 3.6). This reduces the internal clock rate down to 1 KHz to minimize the power
consumed by the chip while still refreshing the internal dynamic nodes at a suitable rate.
The chip includes a òkeepaliveó circuit which detects when the clock has stopped for more than 2
milliseconds. The chip will automatically go into the power down mode if clock loss is detected. The
keepalive detection circuit can be disabled by setting bit 5 in register 7 (See Section 3.4). NOTE: The chip
will draw up to an Amp of current if the clock is stopped and the keepalive circuit is disabled.
1.10
THE ONE SHOT PULSE GENERATOR
The chip can generate a one-shot pulse which is output on the
OS
pin by writing to address 10. The
pulse can be connected to the
SS
,
AS
, or
GS
sync input pins of GC1012A chips (including itself) to
synchronize the output timing, frequency oscillators, or gain settings of multiple chips.
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