參數(shù)資料
型號: GC1012A-CQ
廠商: Texas Instruments, Inc.
英文描述: DIGITAL TUNER CHIP
中文描述: 數(shù)字調(diào)諧器芯片
文件頁數(shù): 19/30頁
文件大?。?/td> 186K
代理商: GC1012A-CQ
GRAYCHIP,INC.
- 14 -
FEBRUARY 18, 1998
GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
This document contains information which may be changed at any time without notice
3.4
GAIN CONTROL REGISTERS
These registers set the output gain.
ADDRESS 6:
Gain Control Register
BIT
TYPE
NAME
DESCRIPTION
0-7
R/W
F[0:7]
The 8 bit gain fraction.
ADDRESS 7:
Gain Exponent Register
BIT
TYPE
NAME
DESCRIPTION
0-3
R/W
S[0:3]
The 4 bit gain exponent.
4
R/W
GS_MODE
Turns on the synchronous gain mode. See below.
5
R/W
KA_DISABLE
Provided for testability. Turns off the clock loss detect function in the keepalive
circuit. This bit powers up low and should be kept low.
6
R
KA_CK
A read only bit which monitors the 1 KHz (approximate) clock used in the power
down mode (See bit 7, address 9, Section 3.6).
7
R
KA_MODE
This bit will read back high if the chip is in the power down mode, either due to the
loss of clock, or by setting bit 7 in register 9.
The chips input to output gain is set using
F
and
S
according to the formula:
GAIN = 2
(
S
-
B
)
(1+
F
/256)
where
B
is the base gain setting which is a function of the decimation mode of the chip. The unity gain
setting (
S
=
B
and
F
=0) means that a 12 bit DC input will show up in the upper 12 bits of the 16 bit output.
The values of
B
are:
DEC
0 or 1
2
3
4
5
6
7
B
6
5
4
3
2
1
0
The GS_MODE control bit determines when new gain settings are applied to the output. New gain
settings are double buffered so that they can be synchronized with the output words. If GS_MODE is low,
then the gain settings are applied to the output samples immediately after
S
has been loaded. If GS_MODE
is high, then the new gain settings are not used until
GS
goes low.
NOTE: The gain settings must be loaded in the correct order-
F
first and then
S
. The circuit detects
new gain settings by sensing when
S
is loaded. this means that
S
must be loaded even if one only wishes
to change
F
.
Bits 5, 6, and 7 of this register were unused R/W bits in the original GC1012 chip. Applications using
the GC1012A as a GC1012 replacement should ignore these bits when reading address 7.
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