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| 型號： | GC1012A-CQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DIGITAL TUNER CHIP |
| 中文描述： | 數(shù)字調(diào)諧器芯片 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大小： | 186K |
| 代理商： | GC1012A-CQ |
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GRAYCHIP,INC.
- 12 -
FEBRUARY 18, 1998
GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
This document contains information which may be changed at any time without notice
3.2
SYNC MODE REGISTER
The sync mode register controls the action of the
SS
and
AS
sync strobes and how they affect the
chips internal timers, counters, and accumulators.
ADDRESS 4:
Sync Mode Register
BIT
TYPE
NAME
DESCRIPTION
0 (LSB)
R/W
SS_OFF
This bit disables the
SS
input.
1
R/W
AS_ON
Enables the accumulator sync
AS
. Normally the frequency accumulator will free
run. This bit causes the frequency accumulator to be initialized to the contents of
the frequency register when
AS
goes low.
SS
, instead of
AS
, will reset the
accumulator if AS_MUX is set and
SS
is not disabled by SS_OFF.
2
R/W
AS_MUX
Use
SS
for the accumulator sync. The
AS
input is ignored and the
SS
strobe is
used in its place when this bit is set and
SS
is not disabled by SS_OFF. (See
AS_ON and AS_FREQ).
3
R/W
LD_FREQ
Load the frequency register in the digital oscillator with the contents of the
frequency word registers. If left on, this bit will cause the frequency register to load
whenever a frequency word register is changed.
4
R/W
AS_FREQ
Enables the synchronous frequency load mode. When this bit is set and
AS
goes
low, the frequency register will be synchronously loaded with the contents of the
frequency control registers.
SS
, instead of
AS
, will load the frequency register if
AS_MUX is set and
SS
is not disabled by SS_OFF.
5
R/W
SS_DIAG
Enables diagnostic syncs. This bit routes the internal sync to the checksum
generator and to all accumulators and control counters within the chip. This forces
the chip to re-initialize at the start of every sync period. The internal sync period will
be 2
20
clocks if SS_MUX is set, otherwise it will be determined by the period of an
externally provided
SS
strobe.
6
R/W
TEST
Shortens the internal sync counter period from 2
20
clocks to 2
8
clocks. This mode
is used to test chips at the factory.
7 (MSB)
R/W
SS_MUX
Use the sync counters terminal count strobe for the internal sync instead of the
sync input
SS
. The internal sync is output on the
SO
pin.
The operation of these control bits are illustrated in Figure 3.
Figure 3. Sync Controls
SYNC TO
CONTROL COUNTERS
AND
OUTPUT CIRCUITS
DIAGNOSTIC SYNCS
SYNC FREQ
ACCUMULATOR
LOAD FREQ REGISTER
SYNC TO
SO
SS_MUX
AS_FREQ
LD_FREQ
AS_ON
AS
AS_MUX
CK
TEST
SS
SS_OFF
I
SS_DIAG
M
1
0
M
1
0
M
1
0
COUNTER
PERIOD =
{
2
20
IF
TEST
= 0
2
8
IF
TEST
= 1
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