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參數(shù)資料
| 型號(hào)： | GC1012A-CQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DIGITAL TUNER CHIP |
| 中文描述： | 數(shù)字調(diào)諧器芯片 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 186K |
| 代理商： | GC1012A-CQ |
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GRAYCHIP,INC.
- 7 -
FEBRUARY 18, 1998
GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
This document contains information which may be changed at any time without notice
1.11
DIAGNOSTICS
An input ramp generator, a sync period generator, and a checksum generator are provided on the
chip in order to run diagnostic tests. Diagnostics are performed by turning on the ramp generator, enabling
the diagnostic syncs, letting the chip operate for at least 4 sync periods, reading the checksum and
comparing it to its predicted value. A new checksum is generated every sync period. The input ramp
sequence is the same for every sync period and the chip is re-initialized at the beginning of each sync period
so that each checksum should be the same once the chips data path has been flushed. The chip requires
at least 3 sync periods to flush, so the fourth and following checksums should be valid. The test is then
repeated for several different tuning frequencies, decimation settings, and output modes.
The sync period is 2
20
clocks, or approximately 1 million clock cycles, so four sync periods will be
about 4 million clocks. This represents a delay of less than 15 milliseconds for a clock rate of 60 MHz.
The following table lists the expected checksums for four test configurations. All values are in HEX.
CONTROL REGISTER
TEST 1
TEST 2
TEST 3
TEST 4
FREQ
(REG 0,1,2,3)
0000101
0F0F0F0
55AA55A
AA55AA5
SYNC MODE
(REG 4)
A9
A9
A9
A9
FILTER MODE
(REG 5)
82
93
E4
D7
GAIN
FRACTION
(REG 6)
AA
55
00
FF
GAIN
EXPONENT (REG 7)
5
4
3
0
OUTPUT
(REG 8)
16
46
21
80
EXPECTED CHECKSUMS
(REG 11)
64
50
A7
03
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| GC1012A-PQ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL TUNER CHIP |
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| GC1012B-PQA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3V DIGITAL TUNER CHIP |
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