參數(shù)資料
型號(hào)： FW322
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開(kāi)放主機(jī)控制器接口
文件頁(yè)數(shù)： 5/148頁(yè)
文件大?。?/td> 1723K
代理商： FW322
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Lucent Technologies Inc.
5
Data Sheet, Rev. 1
February 2001
FW322
1394A PCI PHY/Link Open Host Controller Interface
Table of Contents
(continued)
Table
Page
Table 52. GUID High Register ............................................................................................................................... 63
Table 53. GUID High Register Description ............................................................................................................ 64
Table 54. GUID Low Register ................................................................................................................................ 65
Table 55. GUID Low Register Description ............................................................................................................. 66
Table 56. Configuration ROM Mapping Register ................................................................................................... 67
Table 57. Configuration ROM Mapping Register Description ................................................................................ 68
Table 58. Posted Write Address Low Register ...................................................................................................... 69
Table 59. Posted Write Address Low Register Description ................................................................................... 70
Table 60. Posted Write Address High Register ..................................................................................................... 71
Table 61. Posted Write Address High Register Description .................................................................................. 72
Table 62. Vendor ID Register ................................................................................................................................ 73
Table 63. Vendor ID Register Description ............................................................................................................. 74
Table 64. Host Controller Control Register ............................................................................................................ 75
Table 65. Host Controller Control Register Description ......................................................................................... 76
Table 66. Self-ID Buffer Pointer Register .............................................................................................................. 77
Table 67. Self-ID Buffer Pointer Register Description ........................................................................................... 78
Table 68. Self-ID Count Register ........................................................................................................................... 79
Table 69. Self-ID Count Register Description ........................................................................................................ 80
Table 70. Isochronous Receive Channel Mask High Register .............................................................................. 81
Table 71. Isochronous Receive Channel Mask High Register Description ........................................................... 82
Table 72. Isochronous Receive Channel Mask Low Register ............................................................................... 83
Table 73. Isochronous Receive Channel Mask Low Register Description ........................................................... 84
Table 74. Interrupt Event Register ......................................................................................................................... 85
Table 75. Interrupt Event Register Description ...................................................................................................... 86
Table 76. Interrupt Mask Register ......................................................................................................................... 88
Table 77. Interrupt Mask Register Description ...................................................................................................... 89
Table 78. Isochronous Transmit Interrupt Event Register ..................................................................................... 90
Table 79. Isochronous Transmit Interrupt Event Register Description .................................................................. 91
Table 80. Isochronous Transmit Interrupt Mask Register ...................................................................................... 92
Table 81. Isochronous Receive Interrupt Event Register ...................................................................................... 93
Table 82. Isochronous Receive Interrupt Event Description ................................................................................. 94
Table 83. Isochronous Receive Interrupt Mask Register ....................................................................................... 95
Table 84. Fairness Control Register ...................................................................................................................... 96
Table 85. Fairness Control Register Description ................................................................................................... 97
Table 86. Link Control Register ............................................................................................................................ 98
Table 87. Link Control Register Description ......................................................................................................... 99
Table 88. Node Identification Register ................................................................................................................ 100
Table 89. Node Identification Register Description ............................................................................................. 101
Table 90. PHY Core Layer Control Register ....................................................................................................... 102
Table 91. PHY Core Layer Control Register Description .................................................................................... 103
Table 92. Isochronous Cycle Timer Register ...................................................................................................... 104
Table 93. Isochronous Cycle Timer Register Description ................................................................................... 105
Table 94. Asychronous Request Filter High Register ......................................................................................... 106
Table 95. Asynchronous Request Filter High Register Description ..................................................................... 107
Table 96. Asynchronous Request Filter Low Register ....................................................................................... 109
Table 97. Asynchronous Request Filter Low Register Description ..................................................................... 110
Table 98. Physical Request Filter High Register ................................................................................................. 112
Table 99. Physical Request Filter High Register Description .............................................................................. 113
Table 100. Physical Request Filter Low Register ............................................................................................... 115
Table 101. Physical Request Filter Low Register Description ............................................................................. 116
Table 102. Asynchronous Context Control Register ........................................................................................... 118
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