參數(shù)資料
型號: FW322
英文描述: 1394A PCI PHY/Link Open Host Controller Interface
中文描述: 1394A端口物理層的PCI /鏈接開放主機控制器接口
文件頁數(shù): 27/148頁
文件大?。?/td> 1723K
代理商: FW322
Lucent Technologies Inc.
27
Data Sheet, Rev. 1
February 2001
FW322
1394A PCI PHY/Link Open Host Controller Interface
Internal Registers
(continued)
Table 12. Latency Timer and Class Cache Line Size Register Description
Header Type and BIST Register
The header type and BIST register indicates the FW322 PCI header type and indicates no built-in self-test.
Table 13. Header Type and BIST Register
Register:
Type:
Offset:
Default:
Header type and BIST register
Read only
0Eh
0000h
Bit
15:8
Field Name
LATENCY_TIMER
Type
RW
Description
PCI Latency Timer.
The value in this register specifies the latency
timer for the FW322, in units of PCI clock cycles. When the FW322 is
a PCI bus initiator and asserts FRAME, the latency timer begins
counting from zero. If the latency timer expires before the FW322
transaction has terminated, then the FW322 terminates the transac-
tion when its GNT is deasserted.
Cache Line Size.
This value is used by the FW322 during memory
write and invalidate, memory read line, and memory read multiple
transactions.
7:0
CACHELINE_SZ
RW
Bit
Field
Name
BIST
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HEADER_TYPE
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相關代理商/技術參數(shù)
參數(shù)描述
FW32206 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW322061394 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW32206T100 制造商:AGERE 制造商全稱:AGERE 功能描述:1394a PCI PHY/Link Open Host Controller
FW323 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface
FW32305 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface