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參數(shù)資料
| 型號(hào)： | FW322 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口 |
| 文件頁(yè)數(shù)： | 127/148頁(yè) |
| 文件大小： | 1723K |
| 代理商： | FW322 |
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Lucent Technologies Inc.
127
Data Sheet, Rev. 1
February 2001
FW322
1394A PCI PHY/Link Open Host Controller Interface
Internal Registers
(continued)
Table 111. Isochronous Receive Context Control Register Description
Bit
31
Field Name
bufferFill
Type
RSC
Description
When this bit is set, received packets are placed back-to-back to com-
pletely fill each receive buffer. When this bit is cleared, each received
packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1,
then this bit must also be set to 1. The value of this bit must not be
changed while bit 10 (active) or bit 15 (run) is set.
When this bit is 1, received isochronous packets include the complete
4-byte isochronous packet header seen by the link layer. The end of the
packet is marked with an xferStatus in the first doublet, and a 16-bit
timeStamp indicating the time of the most recently received (or sent)
cycleStart packet. When this bit is cleared, the packet header is stripped
off of received isochronous packets. The packet header, if received,
immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set.
When this bit is set, the context begins running only when the 13-bit
cycleMatch field (bits 24:12) in the isochronous receive context match
register matches the 13-bit cycleCount field in the cycleStart packet. The
effects of this bit, however, are impacted by the values of other bits in
this register. Once the context has become active, hardware clears this
bit. The value of this bit must not be changed while bit 10 (active) or bit
15 (run) is set.
When this bit is set, the corresponding isochronous receive DMA context
receives packets for all isochronous channels enabled in the isochro-
nous receive channel mask high and isochronous receive channel mask
low registers. The isochronous channel number specified in the isochro-
nous receive DMA context match register is ignored. When this bit is
cleared, the isochronous receive DMA context receives packets for the
channel number specified in the context match register. Only one isoch-
ronous receive DMA context may use the isochronous receive channel
mask registers. If more that one isochronous receive context control reg-
ister has this bit set, then results are undefined. The value of this bit
must not be changed while bit 10 (active) or bit 15 (run) is set to 1.
Reserved.
Bits 27:16 return 0s when read.
This bit is set by software to enable descriptor processing for the context
and cleared by software to stop descriptor processing. The FW322
changes this bit only on a hardware or software reset.
Reserved.
Bits 14:13 return 0s when read.
Software sets this bit to cause the FW322 to continue or resume
descriptor processing. The FW322 clears this bit on every descriptor
fetch.
The FW322 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW322 sets this bit to 1 when it is processing descriptors.
Reserved.
Bits 9:8 return 0s when read.
This field indicates the speed at which the packet was received.
000 = 100 Mbits/s.
001 = 200 Mbits/s.
010 = 400 Mbits/s. All other values are reserved.
Following an INPUT* command, the error or status code is indicated in
this field.
30
isochHeader
RSC
29
cycleMatchEnable
RSCU
28
multiChanMode
RSC
27:16
15
Reserved
run
R
RSCU
14:13
12
Reserved
wake
R
RSU
11
dead
RU
10
9:8
7:5
active
Reserved
spd
RU
R
RU
4:0
event code
RU
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相關(guān)代理商/技術(shù)參數(shù) |
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| FW32206 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
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| FW32206T100 | 制造商:AGERE 制造商全稱:AGERE 功能描述:1394a PCI PHY/Link Open Host Controller |
| FW323 | 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface |
| FW32305 | 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface |
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