參數(shù)資料
型號: FDD26AN06A0
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: N-Channel PowerTrench MOSFET
中文描述: 7 A, 60 V, 0.058 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA
封裝: DPAK-3
文件頁數(shù): 8/11頁
文件大?。?/td> 609K
代理商: FDD26AN06A0
2004 Fairchild Semiconductor Corporation
FDD26AN06A0 Rev. A
F
PSPICE Electrical Model
.SUBCKT FDD26AN06A0 2 1 3 ; rev July 2004
Ca 12 8 3.2e-10
Cb 15 14 3.2e-10
Cin 6 8 7.7e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 65.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 4.9e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.5e-9
RLgate 1 9 49
RLdrain 2 5 10
RLsource 3 7 25
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 4e-3
Rgate 9 20 3.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 7e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*110),2.7))}
.MODEL DbodyMOD D (IS=3.8E-12 N=1.06 RS=4.2e-3 TRS1=2e-3 TRS2=1.1e-6
+ CJO=5.8e-10 M=0.53 TT=2.5e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=1.8 TRS1=1e-4 TRS2=-1e-6)
.MODEL DplcapMOD D (CJO=2.13e-10 IS=1e-30 N=10 M=0.43)
.MODEL MmedMOD NMOS (VTO=3.4 KP=2.8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.8)
.MODEL MstroMOD NMOS (VTO=4.1 KP=21 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.96 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=38 RS=0.1)
.MODEL RbreakMOD RES (TC1=9e-4 TC2=-6e-7)
.MODEL RdrainMOD RES (TC1=7e-4 TC2=3.3e-5)
.MODEL RSLCMOD RES (TC1=2.5e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=9e-3 TC2=9e-6)
.MODEL RvthresMOD RES (TC1=-4e-3 TC2=-1e-5)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2.0)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
-
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
19
VBAT
RVTHRES
IT
17
18
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
3
11
7
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
51
10
5
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
6
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