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參數(shù)資料
| 型號： | FDD2512 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | 150V N-Channel PowerTrench MOSFET |
| 中文描述： | 6.7 A, 150 V, 0.42 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252 |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 86K |
| 代理商： | FDD2512 |
FDD2512 Rev B2(W)
)
ON
(
DS
D
R
P
Electrical Characteristics
Symbol
Drain-Source Avalanche Ratings
(Note 2)
W
DSS
Drain-Source Avalanche Energy
I
AR
Drain-Source Avalanche Current
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
I
GSSF
Gate–Body Leakage, Forward
I
GSSR
Gate–Body Leakage, Reverse
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
T
A
= 25°C unless otherwise noted
Test Conditions
Parameter
Min
Typ
Max
Units
Single Pulse,V
DD
= 75 V, I
D
= 2.2A
90
2.2
mJ
A
V
GS
= 0 V, I
D
= 250
μ
A
I
D
= 250
μ
A, Referenced to 25
°
C
150
V
Breakdown Voltage Temperature
147
mV/
°
C
V
DS
= 120 V,
V
GS
= 20 V,
V
GS
= –20 V,
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
1
μ
A
nA
nA
100
–100
(Note 2)
V
DS
= V
GS
, I
D
= 250
μ
A
I
D
= 250
μ
A, Referenced to 25
°
C
2
2.6
–5.6
4
V
Gate Threshold Voltage
mV/
°
C
V
GS
= 10 V, I
D
= 2.2 A
V
GS
= 6 V,
V
GS
= 10 V, I
D
= 2.2 A,T
J
= 125
°
C
V
GS
= 10 V,
V
DS
= 10 V
V
DS
= 10 V,
I
D
= 2.2 A
I
D
= 2.0 A
307
322
606
420
470
870
m
I
D(on)
g
FS
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
Switching Characteristics
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
On–State Drain Current
Forward Transconductance
5
A
S
6.5
344
22
9
pF
pF
pF
V
DS
= 75 V,
f = 1.0 MHz
V
GS
= 0 V,
(Note 2)
6.5
3.5
22
4
8
1.5
2.3
13
7
33
8
11
ns
ns
ns
ns
nC
nC
nC
V
DD
= 75 V,
V
GS
= 10 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 75 V,
V
GS
= 10 V
I
D
= 2.2 A,
3.2
1.2
A
V
V
GS
= 0 V,
I
S
= 3.2 A
(Note 2)
0.8
Notes:
1.
R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) R
θ
JA
= 40°C/W when mounted on a
1in
2
pad of 2 oz copper
Scale 1 : 1 on letter size paper
b) R
= 96°C/W when mounted
on a minimum pad.
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3.
Maximum current is calculated as:
where P
D
is maximum power dissipation at T
C
= 25°C and R
DS(on)
is at T
J(max)
and V
GS
= 10V. Package current limitation is 21A
F
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