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參數(shù)資料
| 型號(hào)： | FDC37B78X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 203/258頁(yè) |
| 文件大小： | 1091K |
| 代理商： | FDC37B78X |
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203
NAME
REG
INDEX
0xC6 R/W
DEFINITION
STATE
Ring Filter Select
Register
Default = 0x00 on
Vbat POR
Note 3
This register is used to select the operation of the
ring indicator on the nRI1, nRI2 and nRING pins.
Bit[0]: 1=Enable detection of pulse train of
frequency 15Hz or higher for 200msec and
generate an active low pulse for its duration to use
as the ring indicator function on nRING pin. The
leading high-to-low edge is the trigger for the ring
indication.
0=Ring indicate function is high-to-low transition
on the nRING pin.
Bit[1]: 1=Enable detection of pulse train of
frequency 15Hz or higher and generate an active
low pulse for its duration to use for 200msec as
the ring indicator function on nRI1 pin. The
leading high-to-low edge is the trigger for the ring
indication.
0=Ring indicate function is high-to-low transition
on the nRI1 pin.
Bit[2]: 1=Enable detection of pulse train of
frequency 15Hz or higher and generate an active
low pulse for its duration to use for 200msec as
the ring indicator function on nRI2 pin. The
leading high-to-low edge is the trigger for the ring
indication.
0=Ring indicate function is high-to-low transition
on the nRI2 pin.
Bits[7:3] Reserved
C
Note 1: There are three types of events Type 1, Type 2 and Type 3.
Type 1: This is an event that comes from a pin or internal signal to the chip. This needs to be
edge detected and latched until cleared by a read of the register. The output of the latch is used to
turn on the power supply through the “or” logic.
Type 2:This is an event that comes from a pin or internal signal to the chip. This does not need to
be edge detected and latched. Cleared at the source.
Type 3: This is an event that comes from a pin or internal signal to the chip. This needs to be
edge detected and latched until cleared by a read of the register. The output of the latch is not
used to turn on the power supply through the “or” logic.
Note 2: nWRTPRT (to the FDC Core) = (nDS0 AND FORCE WRTPRT 0) OR nWRTPRT (from the
FDD Interface). The Force Write Protect 0 bit also applies to the Parallel Port FDC. This bit applies to
both drives.
Note 3: The ring wakeup filter will produce an active low pulse for the period of time that nRING, nRI1
and/or nRI2, nRI1 and/or nRI2 is toggling.
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