參數(shù)資料
型號(hào)： EVAL-ADAU1401EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/52頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1401
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻編解碼器
嵌入式： 是，DSP
已用 IC / 零件： ADAU1401
主要屬性： 在 50-MIPS 時(shí)的 28/56 位音頻處理器，2 ADC，4 DAC
次要屬性： 均衡，交叉，低音增強(qiáng)，多頻帶動(dòng)態(tài)處理，延遲等
已供物品： 2 個(gè)板，線纜，電源
ADAU1401
Data Sheet
Rev. C | Page 12 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
AVDD
PLL_LF
PVDD
PGND
MCLKI
OSCO
RSVD
MP2
MP3
MP8
MP9
DGND
DV
DD
MP
7
MP
6
MP
10
V
DRI
V
E
IOV
D
MP
11
ADDR1/
CDA
T
A/
W
B
CL
AT
C
H/
W
P
S
DA/
CO
UT
S
CL
/CCL
K
DV
DD
AGND
ADC0
ADC_RES
ADC1
RESET
SELFBOOT
ADDR0
MP4
MP5
MP1
MP0
DGND
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
AV
D
FIL
T
A
VO
U
T
0
VO
U
T
1
VO
U
T
2
VO
U
T
3
AG
ND
FIL
T
D
CM
PL
L
_M
O
D
E1
PL
L
_M
O
D
E0
AG
ND
ADAU1401
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
06
75
2-
0
7
Figure 7. 48-Lead LQFP Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 37, 42
AGND
PWR
Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. AGND should be decoupled to an AVDD pin with a 100 nF
capacitor.
2
ADC0
A_IN
Analog Audio Input 0. Full-scale 100 μA rms input. Current input allows input voltage level
to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input.
3
ADC_RES
A_IN
ADC Reference Current. The full-scale current of the ADCs can be set with an external 18 kΩ
resistor connected between this pin and ground. See the Audio ADCS section for details.
4
ADC1
A_IN
Analog Audio Input 1. Full-scale 100 μA rms input. Current input allows input voltage level
to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input. See
the Audio ADCS section for details.
5
RESET
D_IN
Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1401 exits
reset on a low-to-high edge. For more information about initialization, see the Power-Up
Sequence section for details.
6
SELFBOOT
D_IN
Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting
this pin high initiates a self-boot operation when the ADAU1401 is brought out of a reset. This
pin can be tied directly to the control voltage or pulled up/down with a resistor. See the
Self-Boot section for details.
7
ADDR0
D_IN
I2C and SPI Address 0. In combination with ADDR1, this pin allows up to four ADAU1401s
to be used on the same I2C bus and up to two ICs to be used with a common SPI CLATCH
signal. See the I2C Port section for details.
8
MP4
D_IO
Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK). See the Multipurpose Pins
section for more details.
9
MP5
D_IO
Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK). See the Multipurpose Pins
section for more details.
10
MP1
D_IO
Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0). See the Multipurpose Pins
section for more details.
11
MP0
D_IO
Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1). See the Multipurpose Pins
section for more details.
12, 25
DGND
PWR
Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. DGND should be decoupled to a DVDD pin with a 100 nF
capacitor.
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